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gem5
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This is the complete list of members for ArmISA::TLB, including all inherited members.
| _attr | ArmISA::TLB | protected |
| _flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, bool ignore_asn, uint8_t target_el) | ArmISA::TLB | private |
| _params | SimObject | protected |
| aarch64 | ArmISA::TLB | protected |
| aarch64EL | ArmISA::TLB | protected |
| accesses | ArmISA::TLB | protected |
| AlignByte enum value | ArmISA::TLB | |
| AlignDoubleWord enum value | ArmISA::TLB | |
| alignFaults | ArmISA::TLB | mutableprotected |
| AlignHalfWord enum value | ArmISA::TLB | |
| AlignmentMask enum value | ArmISA::TLB | |
| AlignOctWord enum value | ArmISA::TLB | |
| AlignQuadWord enum value | ArmISA::TLB | |
| AlignWord enum value | ArmISA::TLB | |
| AllowUnaligned enum value | ArmISA::TLB | |
| ArmFlags enum name | ArmISA::TLB | |
| ArmTranslationType enum name | ArmISA::TLB | |
| asid | ArmISA::TLB | protected |
| BaseTLB(const Params *p) | BaseTLB | inlineprotected |
| checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) | ArmISA::TLB | private |
| checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) | ArmISA::TLB | |
| checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, ThreadContext *tc) | ArmISA::TLB | |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| cpsr | ArmISA::TLB | protected |
| currentSection() | Serializable | static |
| curTranType | ArmISA::TLB | protected |
| dacr | ArmISA::TLB | protected |
| demapPage(Addr vaddr, uint64_t asn) override | ArmISA::TLB | inlinevirtual |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| directToStage2 | ArmISA::TLB | protected |
| domainFaults | ArmISA::TLB | mutableprotected |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() override | ArmISA::TLB | virtual |
| drainState() const | Drainable | inline |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| Execute enum value | BaseTLB | |
| finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const | ArmISA::TLB | |
| find(const char *name) | SimObject | static |
| flushAll() override | ArmISA::TLB | inlinevirtual |
| flushAllNs(bool hyp, uint8_t target_el, bool ignore_el=false) | ArmISA::TLB | |
| flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el=false) | ArmISA::TLB | |
| flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) | ArmISA::TLB | |
| flushedEntries | ArmISA::TLB | mutableprotected |
| flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el) | ArmISA::TLB | |
| flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) | ArmISA::TLB | |
| flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) | ArmISA::TLB | |
| flushTlb | ArmISA::TLB | mutableprotected |
| flushTlbAsid | ArmISA::TLB | mutableprotected |
| flushTlbMva | ArmISA::TLB | mutableprotected |
| flushTlbMvaAsid | ArmISA::TLB | mutableprotected |
| getAttr() const | ArmISA::TLB | inline |
| getMasterPort() override | ArmISA::TLB | virtual |
| getProbeManager() | SimObject | |
| getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) | ArmISA::TLB | |
| getsize() const | ArmISA::TLB | inline |
| getTableWalker() | ArmISA::TLB | inline |
| getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType) | ArmISA::TLB | |
| haveLargeAsid64 | ArmISA::TLB | protected |
| haveLPAE | ArmISA::TLB | protected |
| haveVirtualization | ArmISA::TLB | protected |
| hcr | ArmISA::TLB | protected |
| hits | ArmISA::TLB | protected |
| HypMode enum value | ArmISA::TLB | |
| init() override | ArmISA::TLB | virtual |
| initState() | SimObject | virtual |
| insert(Addr vaddr, TlbEntry &pte) | ArmISA::TLB | |
| inserts | ArmISA::TLB | mutableprotected |
| instAccesses | ArmISA::TLB | protected |
| instHits | ArmISA::TLB | mutableprotected |
| instMisses | ArmISA::TLB | mutableprotected |
| invalidateMiscReg() | ArmISA::TLB | inline |
| isHyp | ArmISA::TLB | protected |
| isPriv | ArmISA::TLB | protected |
| isSecure | ArmISA::TLB | protected |
| isStage2 | ArmISA::TLB | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, uint8_t target_el) | ArmISA::TLB | |
| m5opRange | ArmISA::TLB | protected |
| memInvalidate() | BaseTLB | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| miscRegContext | ArmISA::TLB | protected |
| miscRegValid | ArmISA::TLB | protected |
| misses | ArmISA::TLB | protected |
| Mode enum name | BaseTLB | |
| MustBeOne enum value | ArmISA::TLB | |
| name() const | SimObject | inlinevirtual |
| nmrr | ArmISA::TLB | protected |
| NormalTran enum value | ArmISA::TLB | |
| notifyFork() | Drainable | inlinevirtual |
| Params typedef | SimObject | |
| params() const | ArmISA::TLB | inline |
| permsFaults | ArmISA::TLB | mutableprotected |
| ppRefills | ArmISA::TLB | protected |
| prefetchFaults | ArmISA::TLB | mutableprotected |
| printTlb() const | ArmISA::TLB | |
| prrr | ArmISA::TLB | protected |
| rangeMRU | ArmISA::TLB | protected |
| Read enum value | BaseTLB | |
| readAccesses | ArmISA::TLB | protected |
| readHits | ArmISA::TLB | mutableprotected |
| readMisses | ArmISA::TLB | mutableprotected |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() override | ArmISA::TLB | virtual |
| regStats() override | ArmISA::TLB | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetStats() | SimObject | virtual |
| S12E0Tran enum value | ArmISA::TLB | |
| S12E1Tran enum value | ArmISA::TLB | |
| S1CTran enum value | ArmISA::TLB | |
| S1E0Tran enum value | ArmISA::TLB | |
| S1E1Tran enum value | ArmISA::TLB | |
| S1E2Tran enum value | ArmISA::TLB | |
| S1E3Tran enum value | ArmISA::TLB | |
| S1S2NsTran enum value | ArmISA::TLB | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| scr | ArmISA::TLB | protected |
| sctlr | ArmISA::TLB | protected |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ArmISA::TLB | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setAttr(uint64_t attr) | ArmISA::TLB | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| setMMU(Stage2MMU *m, MasterID master_id) | ArmISA::TLB | |
| setTestInterface(SimObject *ti) | ArmISA::TLB | |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| size | ArmISA::TLB | protected |
| stage2Mmu | ArmISA::TLB | protected |
| stage2Req | ArmISA::TLB | protected |
| stage2Tlb | ArmISA::TLB | protected |
| startup() | SimObject | virtual |
| table | ArmISA::TLB | protected |
| tableWalker | ArmISA::TLB | protected |
| takeOverFrom(BaseTLB *otlb) override | ArmISA::TLB | virtual |
| test | ArmISA::TLB | protected |
| testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) | ArmISA::TLB | |
| testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level) | ArmISA::TLB | |
| TLB(const ArmTLBParams *p) | ArmISA::TLB | |
| TLB(const Params *p, int _size, TableWalker *_walker) | ArmISA::TLB | |
| translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, ArmTranslationType tranType=NormalTran) | ArmISA::TLB | |
| translateComplete(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType, bool callFromS2) | ArmISA::TLB | |
| translateFs(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false) | ArmISA::TLB | |
| translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr) | ArmISA::TLB | |
| translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, ArmTranslationType tranType=NormalTran) | ArmISA::TLB | |
| translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) | ArmISA::TLB | |
| translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType=NormalTran) | ArmISA::TLB | |
| trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain) | ArmISA::TLB | |
| ttbcr | ArmISA::TLB | protected |
| unserialize(CheckpointIn &cp) override | ArmISA::TLB | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateMiscReg(ThreadContext *tc, ArmTranslationType tranType=NormalTran) | ArmISA::TLB | protected |
| UserMode enum value | ArmISA::TLB | |
| vmid | ArmISA::TLB | protected |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) | ArmISA::TLB | |
| Write enum value | BaseTLB | |
| writeAccesses | ArmISA::TLB | protected |
| writeHits | ArmISA::TLB | mutableprotected |
| writeMisses | ArmISA::TLB | mutableprotected |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
| ~TLB() | ArmISA::TLB | virtual |