FastSim -- Memoizing Micro-Architecture Simulation

Processor simulation, an essential part of micro-architecture research and development, is increasingly slow due to the increased complexity of processor designs. Memoization (an optimization commonly used with functional programming languages) can greatly accelerate complex micro-architecture simulation. For example, FastSim v.1 simulates a detailed out-of-order micro-architecture using memoization, and runs an order of magnitude faster than contemporary out-of-order simulators.

This has been the thesis of my doctoral work at the University of Wisconsin-Madison. A PDF copy of my dissertation can be downloaded from here. This work includes:

• FastSim v.1 -- Version 1 is a memoizing, out-of-order processor simulator. It was written in C and hand crafted to use memoization. It models a detailed out-of-order pipeline, non-blocking data caches, branch prediction, and speculative execution. With memoization, it runs 8-15 times faster than the SimpleScalar out-of-order simulator, previously one of the fastest out-of-order simulators available.
  
  
• FastSim v.2 -- Version 2 is a programming language, compiler, and run-time environment for writing instruction-level micro-architecture simulators with memoization. It makes memoization more accessible to simulator writers, by analyzing and optimizing simulator code automatically.
  
  
• Facile -- This is the FastSim v.2 Architecture Simulation Language. It is designed to both simplify instruction-level micro-architecture simulator implementation, and to simplify the compiler analyses needed to generate memoizing simulators automatically.

Follow one of the links above to learn more about FastSim v.1, v.2, or Facile. A snapshot of the FastSim v.2 source code is available for download here.

Related Publications

• Eric Schnarr, Mark Hill, and James Larus, "Facile: A Language and Compiler For High-Performance Processor Simulators," in the ACM SIGPLAN 2001 Conference on Programming Language Design and Implementation (PLDI01), Snowbird, Utah, June 20-22, 2001. (Slides from the PLDI'01 presentation.)
  
  
• Eric Schnarr, Applying Programming Language Implementation Techniques To Processor Simulation, Ph.D. Dissertation, University of Wisconsin-Madison, Computer Sciences Department, Fall 2000.
  
  
• Eric Schnarr and James Larus, "Fast Out-Of-Order Processor Simulation Using Memoization," in the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, California, October 4-7, 1998. (Slides from the ASPLOS-VIII presentation.)