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UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department
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CS 537
Fall 2012
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| Barton Miller
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Quiz #9
Wednesday, November 20
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Paging and TLB's
Consider a virtual memory architecture with the following parameters
(note that these are the same parameters from Quiz #8):
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64 bit virtual addresses
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256 kilobyte (KB) page size
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256 terabytes (TB) of real memory
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first and second level page tables are stored in real memory (RAM)
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all page tables can start only on a page boundary
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second level page tables will have a maximum size of 64M entries.
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there are no permission or other extra bits.
Design the TLB for the memory mapping architecture that is described above.
This cache should be
4-way set associative
and have
1024 rows.
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On the blank page draw a diagram of the TLB,
showing the size of each field in the TLB.
Indicate how bits of the VA are used for input to the TLB, and describe the
outputs from the TLB.
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Describe what features you would need to add to your TLB to prevent the TLB from being
flushed on each context switch?
Describe any other changes that you would have to make to the processor.
You would need to add a "process ID" field to the the TLB tag field.
You would also need to have a "process ID" field in the processor status
word. This field in the PSW would be loaded with the current process'
ID on each context switch.
For your reference, here are the memory mapping tables from the last quiz:
And here is the diagram for the TLB:
Last modified:
Mon Nov 19 22:17:03 CST 2012
bart