Makefiles

What are they and what are they for?

You might have noticed that it takes a lot of typing to compile a program with multiple source files (e.g. main.m, List.h, List.m, etc.). Furthermore, if you have enough lines of source code, it can take a long time for the compiler to actually compile all of them.

There is a program called make which will let you automagically compile all of your source files by just typing (what else?) make. Furthermore, if you've only changed some of the files, it will only recompile those source files which depend upon files in which you have made changes.

Of course, you have to tell make which files depend on which other files by creating a file called Makefile.

How do I write a Makefile?

Find someone else's Makefile and then pattern-match and modify. At least that's what most people do. I used to do that too until I read about Makefiles in Steve Oualline's Practical C Programming (published by O'Reilly & Associates, purveyors of great reference books for computer systems).

There are four basic types of statements in a Makefile:

Comments

Any line beginning with a # is a comment and will be ignored.

Macros

Macros take the form:

name = data

These are interpreted similar to #define statements in ANSI C. All instances of $(name) in the following statements are replaced by data. For example, if the following macro:

SRC = main.m

causes the following line:

gcc $(SRC)

to be interpreted like so:

gcc main.m

Explicit rules

Explicit rules tell make which files depend on the compilation of other files, and the commands required to compile a particular file. They take the following form:

targetfile : sourcefiles
	commands           # There is a TAB character before each command.

This rule says that in order to create the targetfile, make must perform the listed commands on sourcefiles. For example, the rule:

main: main.m List.h
	gcc -o main main.m List.h

means that in order to create the target file main, the source files main.m and List.h have to exist, and make should use the command:

gcc -o main main.m List.h

to create it.

Implicit rules

Implicit rules are just like explicit rules, except listed without commands. make uses the suffixes on the files to determine what command to perform. For example, the implicit rule:

test.o: test.c io.h

will cause the following command to be executed:

$(CC) $(CFLAGS) -c test.c io.h

Example Makefile

# The following lines are required because standard make does not
# recognize the Objective-C .m suffix.

.SUFFIXES: .o .m
.m.o:
        $(CC) -c $(CFLAGS) $< 


# Macros

CC = gcc
CFLAGS = -g
LIBS = -lobjc
SRC=main.m Person.m Student.m Teacher.m
OBJ=main.o Person.o Student.o Teacher.o


# Explicit rule

hist: $(OBJ)
	$(CC) $(CFLAGS) -o main $(OBJ) $(LIBS)


# Implicit rules

Person.o: Person.h Person.m
Student.o: Person.h Student.h Student.m
Teacher.o: Person.h Teacher.h Teacher.m
main.o: Student.h Teacher.h

There is much more that you can learn about make and Makefiles. Type man make for more information. Back to the index of information about Objective-C.

Michael Chui
mchui@cs.indiana.edu