Full Custom Layout: 16-Bit Multiplier

Bhavesh Mehta, Umair Saeed, Elliot Zastrow, Luke Nelson

Abstract: In this project we designed and laid out 16-Bit Multiplier for TSMC 0.35u process. We chose to implement Ripple Adder as key component for best speed/area trade-off. Following are the snapshots of schematic and layout.

One BitSlice Schematic
Full Design  Schematic

Control  IC Layout
FullAdder Layout
FlopsWithControl Layout
TwoFlops Layout
Buffers Layout
OneBitSlice Layout
FullDesign Layout