Non Uniform Cache Architectures for Wire Delay
Dominated Caches
Abhishek Desai,
Bhavesh
Mehta,
Devang Sachdev,
Gilles Muller
Abstract:
We studied and verified the
paper “An Adaptive , Non Uniform Cache Structure for Wire-Delay
Dominated On-Chip Caches” by Changkyu Kim, Doug Burger and Stephen W.
Keckler. Wire delays continue to grow as the dominant component
of latency for large caches. By exploiting the variation in access time
across widely-spaced subarrays, NUCA allows fast access to close
subarrays while retaining slow access to far subarrays. This
report mainly discusses the issues involved with Dynamic - NUCA.
We basically implemented the D-NUCA into the
Sim – alpha simulator and ran
various integer and floating
point benchmarks on it to compare the D-NUCA IPC with the IPC of
the default cache (UCA) in the Sim-alpha simulator. We found that IPC
does increase with D-NUCA although the IPC of the default UCA was
rather optimistic since wire delays and latch delays were not accounted
for in the default design.
Available as:
Postscript /
MSWord the final
project report. Also presentation slides over here.
Also available as
Postscript
/ MSWord
the
project1 report.