Extra Credit Question (4 points)
Without explicitly setting it, which IEEE rounding method is a program likely to utilize? And, (very briefly) why that particular rounding method?

Question 1 (8 points total, with 4 points for each part)
A fragment of TAL assembly language code is given by:

while:  bgtz $9, end_while
        add  $8, $9, $10
        add  $9, $10, $11
        add  $10, $11, $12
	beq  $0, $0, while   # an unconditional branch
end_while:

bgtz $9, end_while
end_while is +5 instructions
+5 -1 (for updated PC)
+4 instructions
4*4 = +16 addresses (word addressable)

16 = 10000 
remove least significant two zeros
offset = 100 = 4

beq $0, $0, while
while is -4 instructions
-4 -1 (for updated PC)
-5 instructions
-5*4 = -20 addresses (word addressable)

20 = 10100, -20 =  101100
remove least significant two zeros
offset = 1011 = -5

Question 2 (6 points)
Write a TAL assembly language synthesis (not machine code) for following MIPS assembly language instruction. The value that goes into register $2 ($v0) for putc is 11.

     putc  $8
     
     
     addi $2, $0, 11
     add  $4, $8, $0
     syscall

Question 3 (6 points total, with 3 points for each part)
PART A
Is the kernel we used and modified for Assignment 6 intended to be reentrant or nonreentrant?

nonreentrant

reentrant

Question 4 (20 points total, with 4 points for each step)
List the 5 hardware steps that must be accomplished between instructions just before an interrupt is taken and handled. One of these 5 must occur after the other 4; list that one as number 5. Give enough information to demonstrate your complete knowledge of which bits change to what values, and where the bits are. Please do not explain why the bits change.

Set excCode for Cause
(set bits 5 thru 2 of cause register to c0 $13
0000 -> interupt, 1000-> syscall, 1100 -> arithmetic overflow)
Save PC in EPC
(c0 $14 is EPC)
Disable further interrupts
(status register, c0 $12, bit 0 changed to 0)
Change to kernel mode
(status register, c0 $12, bit 1 changed to 0
Pc gets address 0x80000080

Question 5 (10 points total, with 5 points for each part)
Simulations of computer system performance are done on two proposed processor designs, each with an L1 cache. One is called system A, and the other is called system B.

On system A, simulation of the benchmark program causes 200,000 cache misses out of a total of the 5,000,000 memory accesses. On system B, the simulation causes 80,000 cache misses out of a total of the 5,000,000 memory accesses.

Part A Are these cache statistics possible, or is the simulation of the benchmark program producing impossible results? Very briefly, justify your answer.

A system miss ratio: 200,000/5,000,000 = .04 = 4%, thus 96% hit ratio
B system miss ratio: 80,000/5,000,000 = .016 = 1.6%, this 98.4% hit ratio
These simulations are producing possible result according to class.

System B since it has a higher hit ratio for the given simulation.

Question 6 (10 points total, with 5 points for each part)
An assembly language application contains 12,000 assembly language instructions. It is run to benchmark its execution time. It takes 12 seconds to run. The application's programmer then works on the assembly language code to make it better. After this, the application takes 10 seconds to run.

Part A
What is the speedup?

speedup = 12/10 = 1.2

This is somewhat of a trick question, as the answer is we cannot know how many instructions were removed! 
The number of instructions within the assembly language source code does not imply the number 
of instructions executed at execution time.