Extra Credit (2 points) What program did Mel write for the Royal McBee Computer corporation?

Question 1 (10 points)
Give a TAL assembly language synthesis for the MIPS instruction

    lw   $14, JumpTable($8)

Question 2 (20 points total)
Part A (10 points)
The MIPS assembler calculates the machine code for the instruction

   bgtz   $12, while

   jal    switch_fcn

Question 3 (30 points total)
Part A (6 points)
Is the kernel we used and modified for Assignment 6 intended to be reentrant or nonreentrant?

Part B (6 points)
Which MIPS coprocessor C0 control registers were utilized in our Assignment 6 kernel implementation? Give both name and associated register number.

Part C (6 points)
There was a spin wait loop in the kernel within the getc syscall code. Briefly, why? What functionality did the spin wait loop implement?







Part D (6 points)
What is the mnemonic for the single instruction on the MIPS architecture that must be privileged?



Part E (6 points)
For the instruction identified in Part D, (briefly) what happens if an application's execution fetches and decodes this privileged instruction?

Question 4 (10 points)
To get the most speedup when trying to improve a program, to what should a programmer devote the most effort? Answer with a single, concise sentence.

Question 5 (10 points total)
Part A (5 points)
Is it possible for a computer system with a cache to have a hit ratio of 1.0? Briefly justify your answer.





Part B (5 points)
Assume that a computer system has 2 levels of cache. The L1 cache is closest to the processor; the L2 cache sits between the L1 cache and main memory. Using these variables,

• L1T is the time it takes to do a lookup in the L1 cache.
• L2T is the time it takes to do a lookup in the L2 cache.
• MT is the time it takes to complete a main memory access.
• L1H is the hit ratio for the L1 cache.
• L2H is the hit ratio for the L2 cache.
• L2M is the miss ratio for the L2 cache.
• L1M is the miss ratio for the L1 cache.

Question 6 (20 points total)
The UnRealistic Computer Corporation has designed a computer architecture, and their implementation has a single, direct mapped cache. On this system:

• Addresses are 32 bits.
• There is byte addressibility, and all accesses are to a single byte.
• The block size is 16 bytes.
• The cache holds a total of 1024 bytes in its block frames.

Part B (10 points)
Draw a diagram of this cache. Include (and label) all fields.

Part C (5 points)
Assume that address 0x00ff002f is to be read. Circle where this byte is on the diagram you drew for Part B, assuming that this byte access will result in a cache hit.