CS 354, version A
Spring 2007 		Name:___________________
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Exam 3

No electronic devices may be used while taking this exam. Examples of devices not allowed are calculators, pagers, cell phones, wrist calculators/computers, laptop computers, pocket computers. Each student is allowed one 8.5 by 11 inch sheet of paper with handwritten notes. The notes may be on both sides of the paper.

Show all work, and do any/all calculations on the exam. Extra scratch paper may not be used.

Exam Score
EC = _____ /   4
Q1 = _____ /   8
Q2 = _____ / 16
Q3 = _____ /   5
Q4 = _____ /   8
Q5 = _____ /   6
Q6 = _____ / 17

Total = _____ / 60		 



 


 


 


 



Extra Credit Question (4 points)


Under what circumstance does the kernel we used for Assignment 6
enter a spin wait loop?

 


It enters a spin and wait loop inside the getc handler.  It is waiting for a key to be pressed on the keyboard to be placed in a queue.



< code from kernel >
#
# Getc syscall subhandler -- dequeue a character and return it
#
_k_Getc:
		jal	_k_KBdeQ
		sw	$v0, _k_save_v0
		j	_k_Return
...

# Procedure:	_k_KBdeQ
#
# Description:	dequeue a character from the queue of characters entered on the
#		keyboard
...

#
# If no characters are enqueued, wait for one to arrive; in the mean time,
# make sure the display is updated
#
#		bne	$t0, $t1, _k_KBdeQ_l2
#		sw	$ra, _k_KBdeQ_ra
#		jal	_k_DP_handler
#		jal	_k_KB_handler
#		lw	$ra, _k_KBdeQ_ra
#		j	_k_KBdeQ_l1





 


Question 1 (8 points)



Write a TAL assembly language synthesis for the MIPS assembly language
instruction


     lw  $9, JumpTable($8)




Assume that label JumpTable has been assigned
address 0x0040ab0c by the assembler.





     lui $9, 0x0040
     ori $9, $9, 0xab0c
     add $9, $9, $8
     lw $9, 0($9)





Question 2 (16 points, 4 points for each part)


Use the following representation of MIPS machine code to answer this question.



address         contents
--------------------------

0x00400000      0x34010014

0x00400004      0x03a1e822

0x00400008      0x05200002

0x0040000c      0x00004020

0x00400010      0x2109ffff

0x00400014      0xafa80014

0x00400018      0x3402000a

0x0040001c      0x0000000c



PART A
One of the instructions is a branch instruction.
Draw an arrow from the branch instruction to its branch target,
to show where the instruction would branch to, if the branch were taken. 


PART B
Identify all arithmetic and logical instructions
by placing a plus sign (+) next to each one's
machine code.


PART C
Circle the machine code for the syscall instruction.


PART D
One of these instructions is a load or store instruction.
Identify which one by underlining its machine code,
and give the MIPS assembly language equivalent for this instruction. 


address         contents
--------------------------

0x00400000      0x34010014


0011 0100 0000 0001 0000 0000 00010100
ori $1,$0 20 
+ arithmetic or logic instruction: OR




0x00400004      0x03a1e822


0000 0011 1010 0001 1110 1000 0010 0010
sub $29, $29, $1
+ arithmetic or logic instruction: subtraction



0x00400008      0x05200002


0000 0101 0010 0000 0000 0000 0000 0010
bltz $9, 8
to instruction at 0x00400014


0x0040000c      0x00004020


0000 0000 0000 0000 0100 0000 0010 0000
add $8, $0, $0
+ arithmetic or logic instruction: addition



0x00400010      0x2109ffff


0010 0001 0000 1001 1111 1111 1111 1111
addi $9, $8, -1

+ arithmetic or logic instruction: addition



0x00400014      0xafa80014


1010 1111 1010 1000 0000 0000 0001 0100
sw $8, 20($29)



0x00400018      0x3402000a


0011 0100 0000 0010 0000 0000 0000 1010
ori $2, $0,  10
+ arithmetic or logic instruction: OR



0x0040001c      0x0000000c

0000 0000 0000 0000 0000 0000 0000 1100
(circled) syscall





Question 3 (5 points total)



PART A (2 points)


Name an I/O device which is better handled by
doing DMA transfers
than by using polling and spin wait loops.




disk


PART B (3 points)


Briefly,  why are DMA transfers better than polling
and spin wait loops for this device?



A disk transfers large blocks of data, at a faster speed than other I/O devices.  
The spin and wait and polling is not efficent.  Spin and wait tie up the processor 
and polling would not be done often enough to be efficent.  Block transfers can be 
done a tthe speed of the devie instread of the speed of the OS polling.  





Question 4 (8 points total)

PART A (3 points)


Is the kernel we used for Assignment 6 intended to
be reentrant or nonreentrant?

nonreentrant

PART B (2 points)


While executing the code within a nonreentrant kernel,
are interrupts sometimes enabled or always disabled?

always disabled



PART C (3 points)


Give a single MIPS assembly language instruction that will cause a trap.


syscall:

putc
getc
puts





Question 5 (6 points, 3 points for each part)



An assembly language application contains 1400 assembly language
instructions.
It is run to benchmark its execution time.
It takes 14 seconds to run.
The application's programmer then works on the assembly language code
to make it better.
After this, the application takes 10 seconds to run.

 

PART A


What is the speedup?

 

speedup = new rate / old rate 

        = old execution time / new execution time
        
speedup = 14/10 = 1.4


        

PART B


How many assembly language instructions were removed from this
application to make this improvement?
Briefly justify your answer.




This is somewhat of a trick question, as the answer is we cannot know how many instructions were removed! 
The number of instructions within the assembly language source code does not imply the number 
of instructions executed at execution time.
 



Question 6 (17 points total)



PART A (4 points)
Fill in the blanks:


Pipelining improves performance by increasing the
_ throughput (The rate of task completions)__ of instruction completions.




It does not significantly change the 
_ latency (The time it takes (from beginning to end) to complete a task)__
of each instruction's execution time.



PART B (2 points)


Name the two categories of dependencies.

1. data dependency   2. control dependency




PART C (4 points)


In a single sentence answer,
why do the designers of pipelined processors care about dependencies?

Dependencies cause instructions to be executed at the same time because one instruction depends on another.


PART D (4 points)


Two applications are being executed to benchmark the performance
of a computer system's cache.
One application results in a hit ratio of .92,
and the other application results in a hit ratio of .86.
Are these statistics possible?
Briefly justify your answer.

 Yes.  Each application has a different set of instructions and memory accesses.
Since each application is different the caches that are created will be different and cause 
different hit ratios.


PART E (3 points)


A single cache is added to a computer system. 

This diagram illustrates the address as it is used
by the cache. Identify on this diagram the number of bits
used for each field.


         -------------------------------------------------
         |   tag    |   index #   |  byte within block   |
         -------------------------------------------------





tag: 18 (32-10-4)
index: 10 (takes ten bits to represent 1024)
byte within block: 4 (there are 16 bytes in each frame, so it takes 4 bits to represent 16 unique bytes in each block)