CS 354, version A
Spring 2009 		Name:___________________
ID:___________________
Exam 3
No electronic devices may be used while taking this exam. Examples of devices not allowed are calculators, pagers, cell phones, wrist calculators/computers, laptop computers, pocket computers. Each student is allowed one 8.5 by 11 inch sheet of paper with handwritten notes. The notes may be on both sides of the paper.

Show all work, and do any/all calculations on the exam. Extra scratch paper may not be used.

Exam Score
Q1 = _____ /   6
Q2 = _____ /   8
Q3 = _____ /   6
Q4 = _____ / 10
Q5 = _____ / 14
Q6 = _____ / 16
Total = _____ / 60		 



 




Question 1 (6 points)


Give a TAL assembly language synthesis for the MIPS instruction


    sb   $17, X



Assume that the assembler has assigned 

address 0x0082abcc for variable X. 



 


 


 


 


 


 


 


 


 


 


 




Question 2 (8 points)


The MIPS assembler places the machine code for the instruction



     beq  $8, $12, label300



at address 0x0080aa00.
From the symbol table, the address assigned to
label300
is 0x0080aa68.
Mark ALL of the following statements that are TRUE.

 

___  When this branch is taken, it branches backward within the code.

 

___  When this branch is taken, it branches forward within the code.

 

___  The 16-bit immediate field within the machine code for the
beq
instruction will contain the value 0x001a.

 

___  The 16-bit immediate field within the machine code for the
beq
instruction will contain the value 0x0019.

 

___  The 16-bit immediate field within the machine code for the
beq
instruction will contain the value 0x0064.

 

___  The 16-bit immediate field within the machine code for the
beq
instruction will contain the value 0x0068.

 

___  The machine code for the 
beq
instruction will contain
the address 0x0080aa68.

 

___  The immediate field within the machine code for the
beq
instruction represents a 16-bit, two's complement, word offset.

 

___  The immediate field within the machine code for the
beq
instruction represents a 16-bit, two's complement, byte offset.

 


 



Question 3 (6 points total, 3 points each part)


Part A


Is the kernel we used and modified for Assignment 6 
intended to be reentrant or nonreentrant?

 



Part B


Would the kernel portion of a commercially available operating system be 
reentrant or nonreentrant?

 




Question 4 (10 points)


A new input device is to be added to a MIPS computer system that
uses spin wait loops for its kernel (meaning no interrupts).
The new device provides 1 byte of input data and is memory mapped to location
ND_Data.
The status of this device works the same as the other devices,
and it is memory mapped to location
ND_Status.


Write the MIPS assembly language code that goes in the kernel
to handle getting 1 byte of input data from this new device.
Place the byte into register $v0.


   _k_ND_handler:









   _k_ND_return:      j   _k_return_from_handler






Question 5 (14 points total)


Assume that a MIPS computer system has an exception
handler similar to the one we used and modified for Assignment 6.
The exception handler code is currently running 
because of a keyboard interrupt request, and has
just completed the execution of the first instruction
within the exception handler.


Part A (4 points)


What are the contents of the Program Counter (PC)?

 

Part B (6 points)


Fill in the values of the 6 least significant
bits of the Cause register.

              5      4      3      2      1      0    (bit numbering)
     ------------------------------------------------
           |      |      |      |      |      |      |
           |      |      |      |      |      |      |
     ------------------------------------------------


Part C (4 points)


Fill in the values of the 4 least significant
bits of the Status register.

                       3      2      1      0    (bit numbering)
          --------------------------------------
                    |      |      |      |      |
                    |      |      |      |      |
          --------------------------------------






Question 6 (16 points total)


You are the designer for a direct mapped I-cache in a processor.
The cache must follow these design parameters:




Part A (3 points)


What is the maximum number of instructions that this cache may hold? 

 



Part B (3 points)


When the first instruction within a program is fetched,
will it hit or miss in this cache?

 



Part C (6 points)


What block size do you choose for your design? 
Given this choice, how many instructions are there per block frame?

 


 



Part D (4 points)


How many block frames does your design have?