CS 354, version A
Spring 2011 		Name:_____________________
ID:_____________________
Section:____________
Exam 3
No electronic devices may be used while taking this exam. Examples of devices not allowed are calculators, pagers, cell phones, wrist calculators/computers, laptop computers, pocket computers. Each student is allowed one 8.5 by 11 inch sheet of paper with handwritten notes. The notes may be on both sides of the paper.

Show all work, and do any/all calculations on the exam. Extra scratch paper may not be used.

Exam Score
Q1 = _____ /   10
Q2 = _____ /   25
Q3 = _____ /   10
Q4 = _____ /   30
Q5 = _____ /   25
EC = _____ /     2

Total = _____ /100		 



 




Question 1 (10 points)


Give a TAL assembly language synthesis for the MIPS instruction


    lw   $8, JumpTable($9)


 

Assume that the assembler has assigned address 
0x0040ffec
for label JumpTable.



 


 


 


 


 


 


 


 


 


 




Question 2 (25 points total)


The memory image of a portion of a (nonsense) MIPS assembly language program
is given by






Address
Contents





L1		 
0x2188fffd		





L2		 
0x3c0a0040		





L3		 
0x394afffc		





L4		 
0x8d89fffc		





L5		 
0x0000000c		





L6		 
0x1980fffd		





L7		 
0x0c200fff		





L8		 
0x014b6022		







Part A (5 points)

Within the memory image, circle the machine code
for the conditional branch instruction.

 


 




Part B (8 points)
Disassemble the conditional branch's machine code, and give
an assembly language version of the instruction.
Use the label (not the hexadecimal address), 
as provided by the memory image. 
Write any calculations you need to do,
in order to receive partial credit for an incorrect answer.

 


 


 


 



Part C (6 points)

At what (hexadecimal) address is the syscall instruction?

 


 





Part D (6 points)

Two of the instructions in the memory image represent the synthesis of the
MAL instruction


la  $10, array



What (hexadecimal) address has the assembler assigned for
the symbol (label) array?

 


 


 




Question 3 (10 points)


Two programmers will separately try to improve a program.
In a meeting with the boss, each describes their completed improvements:



The boss has no time to investigate further, and must choose
to release the code improvements of one of the programmers.
Which programmer's modifications should the boss choose? 
Briefly justify this choice.

 


 


 


 






Question 4 (25 points total)

 
Part A (5 points)


Is the kernel we used and modified for Assignment 6 
intended to be reentrant or nonreentrant?

 



Part B (9 points)


All semester, we have utilized a 6-step 
instruction fetch and execute cycle.
Give these 6 steps, in their proper order.

1.

2.

3.

4.

5.

6.

 



Part C (8 points)


Again considering the instruction fetch and execute cycle,
for the reentrant exception handler,
there is an added step, and we numbered it Step 0. 
Detail this step.

 


 


 


 



Part D (3 points)


Is this Step 0 done by the hardware, or by the software? 

 


 


 


 


 





Question 5 (25 points total)


Part A (10 points)


For a computer system with separate I-cache and D-cache,
the I-cache can be much smaller in size than the D-cache,
and still achieve excellent performance, in the form of high hit ratios.
Briefly, why?

 


 





Part B (9 points)


An architecture with a direct mapped cache has


An address is divided into 3 fields, as used by the cache.
On the diagram, identify each of the 3 fields
and specify the number of bits comprising each field.



        --------------------------------------------------------------
        |                   |                    |                   |
        |                   |                    |                   |
        --------------------------------------------------------------





Part C (6 points)


A computer system is designed with the cache given in Part B.
A program running on this computer system
will sequentially read each and every element of a huge array of bytes.
Considering only loads that are accesses to the array,
what is the best hit ratio that this cache can obtain? 

 


 


 


Extra Credit (2 points)
What change to the cache design would you suggest to make the
hit ratio higher (better) for the program given in Part C?