Questions on Addressibility

1. Does the MIPS architecture have byte addressibility or word addressibility?

   The MIPS architecture has byte addressibility. Each byte has its own unique address.

2. Can a byte addressible architecture be designed with little endian byte numbering, but big endian bit numbering?

   Yes. The numbering of bits is independent of the numbering of bytes. A diagram for a 32-bit word might appear as

              3             2 and 1                0         byte numbering
   
         0    1    2                         29   30   31    bit numbering
       -----------------------------------------------------
       |    |    |    |  .   .   .   .   .  |    |    |    |
       -----------------------------------------------------
   

3. Difficult Question. Describe a situtation where having byte addressibility matters, and could result in incorrect program operation.

   Imagine that 2 different computers (with 2 different architectures) are to be used in processing 1 set of data. One computer uses big endian byte numbering, and the other uses little endian byte numbering. Both are byte addressible.

   The first computer writes results to memory. Imagine that these results are bytes of data, but to save on the expensive operation of doing memory transactions, the code is written to pack 4 bytes per word. Then a single store places the word into memory.

   The second computer reads these results in order to further process them. It makes the same sort of optimization, and reads a word of data at a time, in order to reduce the number of memory transactions. But, the bytes of data are not in the correct order.

4. Difficult Question. Write a MAL program that determines whether the architecture that the simulator is running on uses little endian or big endian order.

   Answer not yet completed.