CS 354, version A
Fall 2009 		Name:___________________
ID:___________________
Exam 3
No electronic devices may be used while taking this exam. Examples of devices not allowed are calculators, pagers, cell phones, wrist calculators/computers, laptop computers, pocket computers. Each student is allowed one 8.5 by 11 inch sheet of paper with handwritten notes. The notes may be on both sides of the paper.

Show all work, and do any/all calculations on the exam. Extra scratch paper may not be used.

Exam Score
Q1 = _____ /   6
Q2 = _____ / 12
Q3 = _____ / 20
Q4 = _____ / 14
Total = _____ / 52		 



 




Question 1 (6 points)


Give a TAL assembly language synthesis for the MIPS instruction



    sw   $22, count



Assume that the assembler has assigned 
address 0x008aff00 for variable count. 



 


 


 


 


 


 


 


 


 


 


 




Question 2 (12 points total)


The machine code for a MIPS branch instruction is given by

the hexadecimal value 0x110affe8.
This instruction is placed by the assembler at address 0x0080cc04.





Part A (3 points)


Give the mnemonic for this instruction.

 


 



Part B (3 points)


For a taken branch,
does this branch go forward within the code or backward within the code?

 


 



Part C (6 points)


At what (hexadecimal) address is this branch's target instruction?
Show your work in order to get partial credit in the case of an 
incorrect answer.

 


 


 


 


 


 


 


 


 


 


 



Question 3 (20 points total)


Part A (4 points)


Is the kernel we used and modified for Assignment 6 
intended to be reentrant or nonreentrant?

 



Part B (2 points)


Assume that a MIPS computer system has an exception
handler similar to the one we used and modified for Assignment 6.
The exception handler code is currently running 
because the application fetched and executed a
syscall 
instruction.
The kernel has
just completed the execution of the first instruction
within the exception handler.
What is the value of IEc, the current interrupt enable bit?

 



Part C (2 points)


Using the same assumptions as given in Part B,
what is the value of KUc, the current kernel/user mode bit?

 



Part D (2 points)


Where does the MIPS processor keep these two state bits
(IEc and KUc)?

 


 


 



Part E (10 points)


List the 5 things that the MIPS hardware does (between instructions)
in order to prepare to run the MIPS exception handler.

    

  1. 

     
    

  2. 

     
    

  3. 

     
    

  4. 

     
    

  5. 

     
    

    





Question 4 (14 points total)


You are the designer for an L1, direct-mapped, D-cache in a processor.
The cache must follow these design parameters:




Part A (6 points)


To do a lookup, the cache will divide the address
into 3 fields.
On the diagram identify what each field represents.

      31                                               0   <- little endian bit numbering
     ----------------------------------------------------
     |               |                 |                |
     |               |                 |                |
     ----------------------------------------------------



 



Part B (4 points)


What block size do you choose for your design? 

 


 



Part C (4 points)


Given your answer to Part B, how many block frames does your design have?