What has been ignored so far: how to fit both an opcode and an address in a 32-bit instruction.
First. . .how many bits are "needed" for the opcode?
The number of unique patterns given by n bits is 2^n.
So, the problem boils down to deciding how many unique instructions are necessary (and desired) for a computer.
There are possibly 64 enumerated here, so 6 bits should be enough. That leaves 26 left for a 32-bit address specification.
Oops! For a load/store instruction, we need a register specification also (where the data is to come from/go to). That leaves only 21 bits for an address specification.
A discussion of addressing modes:
The original goal of this discussion was to figure out a way to fit 32-bit addresses into less than 32 bits.
The discussion is going to be expanded a bit to talk about the different ways that an instruction could specify where its operands are.
But first, some ways to specify a 32 bit address:
2 words: the first contains the opcode and other operands the second contains a 32-bit address
This method defeats the whole purpose.
On an architecture that offers operands specified in this way, the addressing mode is called direct. Some architectures will call this addressing mode absolute.
A MAL example of this:
lw $8, ($9)
On an architecture that offers operands specified in this way, the addressing mode is called register direct.
MIPS and most architectures do not have an addressing mode such as this. Therefore, there is no name given to this idea. The Intel x86 architecture allows as limited form of this, limiting which registers can be used.
A MAL example of this:
lw $8, 24($9)
On an architecture that offers operands specified in this way, the addressing mode is called base displacement.
On an architecture that offers operands specified in this way, the addressing mode goes by many different names. A good general name is called PC relative.
This implies that the operand (address of) is located in the same portion of memory as the instruction being executed.
Karen knows of no names for this addressing mode.
Some computers offer more ways of getting at operands. These methods are called addressing modes.
Load/store architectures usually have a VERY limited set of addressing modes available.
Memory to memory architectures often offer LOTS of modes. This flexibility often forces these machines to have variable length instructions.
Here are some common names for addressing modes. (Some are repeated from the list above.) Remember, an addressing mode really gives the information of where an operand is (its address). An instruction decides how to use the address.
A variation might be Register Indirect. The initial address is located in a register (instead of in the instruction).
The MIPS architecture is very carefully designed such that all machine code instructions fit into a maximum of 32 bits. Then, all instructions are exactly 32 bits in size.
Remember the instruction fetch and execute cycle?
Step 2 (update the PC) becomes easy when all instructions
are exactly the same length.
On the MIPS architecture, each byte has a unique address
associated with it (called byte addressibility),
and each instruction fits exactly into 4 bytes.
Therefore, update the PC means add 4 to the PC.
|Copyright © Karen Miller, 2006, 2007, 2008|