The main objective of this problem set is to become familiar with the Mentor CAD tools and the Sun workstations. The "Getting Started with Mentor" handout is available on the CS552-2 Web page. Please go through the handout carefully and completely. Additional Mentor documentation is available on-line as part of the Mentor help system. Try to learn as much as possible about the use of Mentor tools (Design Architect, Design Manager, mgc_acro , and Quicksim II) because you will be using them throughout the semester.

You should simulate your solutions using QuickSim II to both verify the correct function of your designs for yourself and to hand in to me so that I can see that your solutions work. You also have to hand in printouts of the logical layout of your designs (the schematic files) and their external interfaces (a printout of the symbolic version).

This assignment will take a significant amount of time if you are not already familiar with the Mentor CAD tools. Get started as soon as possible.

To deal with complexity, use a "divide and conquer" or hierarchical design approach. Divide the circuit into logical pieces, called blocks, which can be composed to form the larger circuit. For example, a 4-to-1 multiplexor or mux can be composed from 2-to-1 muxes. Hierarchical design reduces both the complexity faced by the designer and the complexity of the computer's representation of the schematic. While hierarchical design may seem unnecessary for something as simple as a 4-to-1 mux, remember that modern computers have millions of gates.

Problem 1

1. Design a 1-bit 2-to-1 multiplexer using only NAND, NOR, and NOT gates. Implement the circuit in Mentor Design Architect. The input data lines of the multiplexer should be labeled InA and InB, the select line labeled S, and the output labeled Out.

2. Create a symbol for the above multiplexer. To see how to do this, refer to Getting Started With Mentor,  Corrections, and other handouts listed in the "Handouts" section of the main web page.

3. Use QuickSim II to exercise the symbolic version of your multiplexer over all possible combinations of inputs. You can do this by applying clocks of different periods to each input and then running the simulation long enough for all combinations to appear. Print the resulting trace and label each set of inputs and the corresponding outputs.You might want to use QuickSim II's "save WDB" feature to save the input waveforms once you have them correct. This makes the test-fix-test cycle easier the second time around. 

4. Use the symbol of the 2-to-1 mux you designed in step 2 to hierarchically create a 4-to-1 mux. Label the inputs InA, InB, InC, and InD, and the output Out. Make your select a bus (not single wires); label it S(1:0)  (If S is 00, InA is selected; if S is 01, InB is selected, etc.) Create a symbol for your 4-to-1 mux.

5. Hierarchically create a quad 4-to-1 mux using the symbolic version of your 4-to-1 mux. The inputs to the new mux should be four 4-bit busses labeled InA(3:0), InB(3:0), InC(3:0), and InD(3:0). The select bus is labeled S(1:0) and the output should be a bus labeled Out(3:0).

6. Test the mux you created using QuickSim II and print out annotated results of your simulations. It is not necessary to exhaustively test all combinations of all 18 input pins, but choose patterns that make it obvious from the resulting trace file that the design is working.

7. Turn in printouts of gate level schematics, top-level symbols, and trace files.

Problem 2

1. Design a 1-bit full adder using only NOT, NAND, NOR, and XOR gates. Label the inputs as 'A', 'B' and 'Cin' (carry-in). Label the outputs as 'S' and 'Cout'.
2. Create a symbolic version of this adder.
3. Use QuickSim II to verify the correctness of the 1-bit adder over all combinations of inputs. Turn in the schematic design, symbolic version and the annotated waveforms.
4. Using the symbolic version of the 1-bit full adder you created above, design a ripple carry adder that adds two 4-bit binary numbers. Make the inputs and outputs be 4-bit busses labeled A(3:0), B(3:0), and SUM(3:0), respectively.  Label the carry in CI and the carry out CO. Create a symbol for the 4-bit ripple carry adder. Using Quicksim II show the results for 8 combinations of values of the two input numbers.  Turn in the schematic design, symbolic version and the annotated waveforms.
5. Using the symbolic version of the 4-bit full adder you created above, design a ripple carry adder that adds two 16-bit binary numbers. Make the inputs and outputs be 16-bit busses labeled A(15:0), B(15:0), and SUM(15:0), respectively.  Label the carry out from the adder CO. Create a symbol for the 16-bit adder. Using Quicksim II show the results for 8 combinations of values of the two input numbers.  Turn in the schematic design, symbolic version and the annotated waveforms.
6. In one or two sentences explain what is the disadvantage of a ripple carry adder?

Problem 3

A sequence detector is a finite state machine that outputs "1" when a particular sequence is detected and outputs "0" otherwise. For example, a sequence detector designed to detect the sequence "1010" outputs "1" every time this sequence is seen in the input stream. Thus, for an input stream "101010" the output will be "000101".

Design a sequence detector that detects the sequence that corresponds to the last two digits in your ID number, represented in binary coded decimal(BCD). For example, if your id is 902 631 9385 , the last two digits being 85, the sequence detector will detect 85, which is 10000101 in BCD. The sequence detector should also detect overlapping sequences.

You should complete each of the following:

• Construct the state diagram of the machine. Turn in the state diagram.
• Implement the sequence detector using Design Architect. Create a symbol for your detector. Turn in printouts of both the circuit level and symbolic versions of your detector.
• Simulate your design using QuickSim II. You should chose an input sequence that shows that your detector works correctly. Be sure to turn in the annotated trace of your simulation and describe why the sequence shows that your detector works properly.
• Please make a note of your ID number.

Design note: You may find that your designs for these problems can produce "glitches" -- short pulses on a wire when no transition was expected. This is OK as long as the signal quickly returns to its correct value and no glitch can be clocked into a latch. You may be tempted to add additional do-nothing gates in order to delay some signals to get rid of the glitch. This is not necessary in general computer design. If you are called upon to produce a truly glitch-free design, e.g. for an asynchronous "ready" strobe or for clock gating, more rigorous techniques are needed anyway.