CS/ECE 552 : Introduction to Computer Architecture
Spring 2006
Prof. Wood
Problem Set #2

Due: Feb 8, 2006 (in class)
Approximate Weight: 20% of homework grade

You should do this assignment in groups of two

LATE ASSIGNMENTS WILL NOT BE ACCEPTED

Problem 1

Design a 16-bit barrel shifter with the interface shown in the figure below. The barrel shifter should have three inputs In(15:0), Cnt(3:0), and Op(1:0) and an output Out(15:0). In(15:0) is the value to be shifted. Cnt(3:0) is the number of bit positions to shift. Op(1:0) is the operation to be performed:

Opcode	Operation
00	rotate left
01	shift left
10	shift right arithmetic
11	shift right logical

Table 1

Your design should use 4-to-1 multiplexers, decoders, and logic gates.

Turn in the schematic design and annotated traces showing the working of your design.

Problem 2

Design a simple 16-bit ALU using Mentor. Operations to be performed are 2's Complement ADD, bitwise-OR, bitwise-XOR, and bitwise-AND. In addition, it must have the ability to invert either of its data inputs before performing the operation and have a C0 input (to enable subtraction). Another input line also determines whether the arithmetic to be performed is signed or unsigned . Use a carry look-ahead adder (CLA) in your design. (Hint: First design a 4-bit CLA. Then use blocks of this CLA for designing the 16-bit CLA.)

Opcode	Function	Result
00	ADD	A+B
01	OR	A OR B
10	XOR	A XOR B
11	AND	A AND B

Table 2

The external interface of the ALU should be:

Inputs:

Data lines A and B (16 bits each.)
A carry-in for the LSB of the adder.
The OP code (2 bits.) The OP code determines the operation to be performed. The opcodes are shown in Table 2.
An invert-A input (active high) that causes the A input to be inverted before the operation is performed.
An invert-B input (active high) that causes the B input to be inverted before the operation is performed.
A signed-or-unsigned input (active high for signed) that indicates whether signed or unsigned arithmetic to be performed for ADD function on the data lines. (This affects the OFL output.)

Outputs:

Data out (16 bits.)
OFL (1 bit.) This indicates high if an overflow occured.
Zero (1 bit.) This indicates that the result is exactly zero.

In case of logic functions, OFL is not asserted (ie. kept logic low). You can assume 2's complement numbers.

Use hierarchical design and simulate each block by itself before you try the complete design.

You should hand in:

1. Schematic sheets and symbol sheets of all the blocks that you designed.
2. Annotated simulation trace output of the complete design. Pick representative cases for your simulation input.

Problem 3

Problem 2.52 on CD of COD3e: In More Depth
Use this instruction sequence instead of the one given:
b = a + a; c = b - d; e = a - c;

Problem 4

Problem 2.57 on CD of COD3e: In More Depth

Problem 5

See page B-43 on CD of COD3e: Chapter/Appendix
Answer the problem using these operands instead of the ones given:
a: 0010 0101 1011 1010 b: 1101 1100 0001 0110

Problem 6

Problem 4.10 on Page 273 of COD3e

Problem 7

Problem 4.11 on Page 274 of COD3e