Problem 1

Consider a single-cycle computer design such as the one in Figure 5.17 of the text (page 307). Assume a MIPS-like instruction set. Suppose you had just completed such a design, and now the compiler group has come to you with a small list of additional instructions they would like you to add. How would you respond? Order the list from easiest to most difficult to add, based on the number of things that would have to change in the datapath; briefly indicate for each one what those changes would be.

1. "Split Register": This instruction would read an operand from $rs and move its lower half to $rd with the upper half set to zero. It would also take the upper half of $rs, shift it right 16 bits (with zero fill), and write it to $rt.
2. "Bit Equal": This instruction does a bit-for-bit compare between two registers. For each bit i, if bit i of $rs is equal to bit i of $rt, set bit i of $rd; otherwise set bit i of $rd to zero.
3. "Replace Under Mask": This instruction uses $rt to select which bits of $rs to replace with bits from the literal field. For each bit of $rt that is a zero, the result comes from the corresponding bit of $rs; for each bit that is a one, the result comes from the sign-extended 16-bit literal. The result is written to $rd.

Problem 2

Using Verilog, design an 8 -by -16- bit register file. Figure 1 gives the high-level interface.  It has one write port, two read ports, three register select inputs (two for read and one for write,) a write enable, a reset and a clock input. All register state changes occur on the rising edge of the clock. As always, your basic building block must be the D-flipflop given here. The read ports should be all combinational logic. Do not use tri-state logic in your design.

                         +--------------------+
                         |                    |
    read1regsel[2:0] >---|                    |----> read1data[15:0]
    read2regsel[2:0] >---|                    |
                         |                    |
    writeregsel[2:0] >---|                    |
     writedata[15:0] >---|                    |----> read2data[15:0]
                         |                    |
               write >---|                    |
                 clk >---|                    |
                 rst >---|                    |
                         +--------------------+

The read and write ports are 16 bits each. The select inputs (read and write) are 3 bits each. When the write enable is asserted (high) the selected register will be written with the data from the write port. The write occurs on the next rising clock edge; write data cannot flow through to a read port during the same cycle.

There is no read enable; data from the selected registers will always appear on to the corresponding read ports.

The reset signal is synchronous and when asserted (active high), resets all the register values to 0.

You must use a hierarchical design. Design a 16-bit register first, and then put 8 of them together with additional logic to build the register file. Create a symbol for your register file. (You do not need symbols for the smaller pieces.) For simulation purposes, any signal that is wider than one bit should be represented as a bus going into or out of your system. For a 16-bit bus, there should not be 16 signals on your trace output.

Use this clock / reset generator. Make it into a symbol, and connect it to your register file symbol in a top-level schematic. Doing this will mean that you do not need use forces to create the clock and reset.

Hand in printouts of all your Verilog, along with your annotated simulation traces. Make sure that every register gets read and written properly, and that each bit of each register has been both low and high at least once. (For example, use patterns such as 5555 and AAAA.) A simultaneous read and write on the same register must work properly, as must a case of read and write at the same cycle but on different registers.

You must also run the Vcheck program on your Verilog source. (Information on this is at the bottom of the VerilogRules page.) You must hand in the output of this program. Since this program is new, it is possible that it will complain about something when it shouldn't; if after careful consideration you believe your Verilog follows the style rules, you may be right. If you believe the rules themselves need debugging, contact the TA.

Problem 3

Using Verilog, write, compile and simulate a six state saturating counter. The counter should take as input a clock and a reset line, and output a 3-bit wide bus. Reset is synchronous and sets the output to 0 at the rising edge of the clock. The output should increment every clock cycle until it reaches its saturation value (5, i.e. 101 in binary) and then continue to output the maximum value until reset.

The reset line is active high, i.e. a logical value of 1 will reset the counter, while a logical value of 0 will let the counter increment.

If reset is high while the counter is still counting, the output should reset to 0. If reset is held high, the counter should hold at 0. All state changes should occur on the clock's rising edge.

Use the same clock / reset generator symbol as in problem 2 to drive clock and reset in your simulation.

Turn in the Verilog code for your design, output of Vcheck, and a simulation which shows the counter working properly.

Problem 4

Implement a sequence detector similar to the one in Homework 1. Use this pattern: 10100110, and this state diagram. Use a minimal number of flipflops. Use Verilog to specify the circuit. Create a symbol containing your design, with three inputs (datain, clk, rst) and two outputs (match and err). (The "err" output is a standard way of indicating hardware errors or illegal states; we'll get in the habit of using it, though in this case it will only be driven if there are states which are supposed to be impossible to get into.)

Use the same clock / reset generator symbol as in problem 2.

Turn in a copy of your Verilog source code, output of Vcheck, and the simulation showing the working of your design.

Problem 5

For this problem, you do not need to use mentor or Verilog; just draw the designs (neatly!) on paper.
First, design a 4-bit ripple-carry adder; as a building block use squares representing full adders. (You may use a printout from Homework 1.)
Next, draw an 8-bit carry-select adder, using as building blocks 4-bit ripple-carry adders and 2:1 muxes.

Now, calculate the delay at output S₅ of the carry-select adder. To do this, you will need to know the gate design of the full adder and the 2:1 mux; these are given here. You will also need to know the delay function:
  AND, OR, NAND, NOR, NOT:  delay = (8 + n²) τ
  XOR:  delay = (12 + n²) τ
where n is the number of inputs to the gate.
Assume that all inputs to your design are available at time zero. Calculate (and mark on your paper) the pertinent critical-path delays through the basic building blocks, through your ripple adder, and finally to S₅ of the entire design.