Problem 1

    Consider a direct-mapped cache with 32-byte blocks and a total capacity of 512 bytes. For the sequence of byte addresses below, indicate which references will result in cache hits and which will result in cache misses. Show the final contents of the address tags at the end of execution.

0x000092e8
0x000092f4
0x00004182
0x0000780a
0x0000a796
0x0000a690
0x0000408e
0x0000a798
0x00007800
0x000092fc
0x00027c02
0x0001478e
0x00004198
0x00006710
0x0000a790
0x0000670c
0x00027c04

Problem 2

Re-do problem 1, but using a two-way set-associative cache. When replacing a block, the least-recently-used block is chosen to be replaced. Everything else (block size and total capacity) remains the same.

Problem 3

Designers may use average memory access time (AMAT) as a way to compare the performance of alternative cache designs. AMAT is the average time to access memory considering both hits and misses and the frequency of different accesses; it is equal to the following:
        AMAT = Time for a hit + (Miss rate x Miss penalty)
Find the AMAT for a processor with a 2 ns clock, a miss penalty of 24 clock cycles, a miss rate of 0.08 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.

Problem 4

Consider a cache with the following characteristics:
32-byte blocks
3-way set associative
512 sets
47-bit addresses
writeback
LRU replacement policy

(a) How many bytes of data storage are there?

(b) What is the total number of bits needed to implement the cache?

(c) Make a picture similar to the one on page 503 of the text. (As with the picture in the text, include the hit and data logic.)

Problem 5

Exercise 7.32 on page 558 of the textbook, except use the following numbers:
        Cache 1: Instruction miss rate 5%; data miss rate 8%.
        Cache 2: Instruction miss rate 3%; data miss rate 6%.
        Cache 3: Instruction miss rate 2%; data miss rate 4%.

Problem 6

Exercise 7.39 on page 559 of the textbook, except assume a 47-bit virtual address, 32KB pages, and a 41-bit physical address.

Problem 7

Use the parity check matrix for a (7,4) Hamming code (m=4, k=3) given in the Error Detection/Correction Handout for the following problem:

(a) Find the codewords for these datawords :
(1) 0110
(2) 1110
(3) 1000
(4) 1101

(b) For this part assume that at most one bit can be in error.
If the following values are read from the memory (stored using the above encoding in the order C₁ C₂ b₁ C₃ b₂ b₃ b₄), find the correct dataword.
(1) 1010011
(2) 1011110
(3) 0101001

(c) For the datawords in part (a), also produce the 8-bit code using a global parity applied to codewords generated using Hamming code. What additional benefit would this code provide?