The report is formal in the sense that it should be typed, well written, and well organized.  A sloppy, poorly written, or error-filled (semantic, spelling, gramatical errors, etc.) report will be penalized.  You need to include the following items in your report:

    Note:  Please clearly label each report section with the number presented below.  Please include them IN ORDER when you turn in your final report.

  1. A brief overview of your design.
  2. A discussion of how you optimized your CPU (this includes the datapath and the control.)
  3. A table listing the possible hazards that arise in your pipelined design and the number of stall cycles that each hazard incurs.
  4. A discussion of what does not work or what you would have liked to have done.  For each part of the implementation that does not work, turn in a trace that demonstrates what the problem is and a discussion of how you found the problem and how you would go about fixing it.
  5. A section outlining what you learned by doing this project.
  6. Printouts of traces that show how many cycles your design took to execute pipeTest and cacheTest.
  7. Printouts and traces of any test assembly code that you wrote to test your design.  These printouts must include comments about what is tested by each section of code.
  8. A state diagram for any state machine controllers in your design.  All other controllers should include a high-level textual description plus verilog code (or schematic, if done in gates).

All printouts should be annotated.

You can include anything else you want in the Appendix.