In this project, you will design a pipelined processor. It will execute the instruction set of the WISC-SP06 ISA. You will work in groups of two (or three, with instructor's permission).

• Project Design and Test Plan - Due March 6 (5% of project grade)
  • Each group needs to turn in a typed report (2-3 page single-spaced) describing your project design and test plan.  You are expected to develop a detailed schedule identifying key milestones and a breakdown of the tasks by project partner. Make sure that your schedule takes into account the remaining homework assignments and your other course obligations (e.g., midterms). In addition to the design, you are expected to develop a detailed test plan, including high-level descriptions of component, module, and system tests.


• Non-Pipelined Design -  Due March 31 (25% of project grade)
  • At this milestone, you are expected to have a correctly functioning non-pipelined design. It should be running the full WISC-SP06 instruction set, except for the extra-credit instructions SIIC and RTI. It should use the single-cycle memory model. Each group will schedule a time to meet in the lab with Professor Wood or with the TA to provide a demonstration of your design. (Signups will be posted a few days before.) Both partners must be present. When we meet, you will hand in a brief status report indicating your progress so far and clearly spelling out any changes in the schedule or work assignments. Attach to this a printout of your entire design so far, and traces that show its correct operation. Be prepared to demonstrate your project running the test programs; you may also be given additional programs to run at the time. Be sure to arrive at the lab early and get prepared; the time for each demo will be limited so we need to have them go smoothly.
  
  
• Pipelined Perfect-Memory Design - Due April 21  (35% of project grade)
  • At this point, the pipelined version of your design needs to be running correctly, but no optimizations are needed yet. Correctly means that it must detect and do the right thing on pipeline hazards (e.g., stall). You will still use the single-cycle memory model. As before, you will sign up for a timeslot to demonstrate your project in the lab. The format is similar to the previous demo but it will probably take a little longer. Have an updated status report to hand in. (A design printout is not needed at this step.) Both partners are required to be present and both are expected to explain and answer questions about the whole design. Answering a question with: "I have no idea, my partner did that" is a failing answer. You must (at least) be able to answer: "My partner implemented that, but it works in the following way....".


• Final Report and Demo - Due May 5th (35% of project grade)
  • This is the third and final lab demo. At this point, you will demonstrate your complete design. This includes the following required items:
    • Two-way set-associative caches and the multi-cycle memory model;
    • Bypassing within the register file
    • Bypassing from the beginning of the M stage to the beginning of the X stage
    • Bypassing from the beginning of the W stage to the beginning of the X stage
    • Branches predicted "not taken"
    • Halt instruction must leave PC pointing at halt+1. Do not let it increment past this address.
  • Also, please demonstrate the extra-credit Instruction Interrupt Counter, if you have done it, plus any other bells & whistles you may have added for additional extra credit
  • As of the morning of the demo, make sure you have the latest version of all tests.
  • At the time of the demo, or at the latest by 4:00 PM that day, turn in your typed final report; see the Project Report document on the web.
  • At the time of the demo, or at the latest by 5:00 PM that day, all Verilog source files must be submitted electronically. (The method for doing this will be specified at a later date.)
  • You must print out the coversheet and staple it over your project report. Fill in your names and have it available for the Professor or TA to check off your tests at the final demo.