After you have successfully made a pipelined version of your processor, the next step will be to make your design capable of handling arbitrary stalls in the memory accesses. To do this, replace your single-cycle memory modules with these "stalling memory" modules. The source of the module is here.

This module has a "ready" output. When "enable" is true, "ready" may be either true (indicating that the requested read or write has been done), or false (indicating that read data is not valid or that a write has not been performed). Your design must keep presenting the same operating to the memory module until the operation succeeds.

                              +-------------+
       data_in[15:0]  >-------|             |--------> data_out[15:0]
          addr[15:0]  >-------|  65536 word |--------> ready
              enable  >-------|  by 16 bit  |
                  wr  >-------|  memory     |
                 clk  >-------|             |
                 rst  >-------|             |
          createdump  >-------|             |
                              +-------------+

Examining the source file stallmem.v, you will see "rand_pat", a shift register which controls the "ready" output. You may wish to arbitrarily modify the initial value of this register in order to try your design with different patterns of stalls.