Tentative Schedule for CS 552, Section 1
Spring 2006

 

Week	Monday	Tuesday	Wednesday	Thursday	Friday
January 16th	MLK jr. Day		Introduction Read COD3e 1 HW 0 Out; HW 1 Out		Instructions I Read COD3e 2.1-2.8
January 23rd	Instructions II Read COD3e 2.9-2.11,2.13, 2.15-2.17		Arithmetic I Read COD3e 3.1-3.5 HW 0 Due; HW 2 Out		Arithmetic II Read COD3e B.5-B.6 (on CD)
January 30th	Performance Read COD3e 4 Supplemental reading		Datapath Read COD3e 5.5.1-5.3 HW 1 Due		Discussion
February 6th	Single-Cycle Control Read COD3e 5.4		Pipelining I Read COD3e 6.1-6.3 HW 2 Due; HW 3 Out		Pipelining II Read COD3e 6.4-6.5
February 13th	Verilog I		NO CLASS (HPCA)		Discussion
February 20th	Pipelining III Read COD3e 6.6, 6.8  Project Description Out		Pipelining IV Read COD3e 6.9-6.11 HW 3 Due; HW 4 Out		No Class
February 27th	Pipelining V/Super Scalar		Multi-cycle Control Read COD3e 5.5		Discussion
March 6th	Exceptions Read COD3e 5.6, 5.9-5.11 Project Plan Due		Midterm Review HW 4 Due	Midterm Exam 7:15-9:15 PM
March 13th	Spring Break
March 20th	Memory I Read COD3e 7.1, 7.2		Memory II Read COD3e 7.3
March 27th	Memory III Read COD3e 7.4 and Error Correction Handout		Memory IV Read COD3e 7.5-7.8 HW 5 Out		Project Demo I: Single-cycle Datapath
April 3rd	Memory V		Multiprocessors I/Slop
April 10th	Arithmetic III Read COD3e 3.6-3.9		Arithmetic IV HW 5 Due; HW 6 Out		I/O I Read COD3e 8.1-8.4
April 17th	No Class		I/O II Read COD3e 8.5-8.10		Project Demo II: Pipelined processor with perfect memory
April 24th	Multiprocessors II Read COD3e 9.1-9.3, 9.7		RAS
May 1st	Final Review HW 6 due				Final Project Demo; Written Reports Due @ 4pm
May 8th				Final Exam Thursday, May 11th 12:25-2:25pm

Readings:

• Should be done BEFORE class

• COD3e =
      David A. Patterson and John L. Hennessy,
      Computer Organization and Design:  The Hardware and Software Interface
      Morgan Kaufmann Publishers, Third Edition. ISBN: 1-55860-604-1