UW-Madison
Computer Sciences Dept.

CS/ECE 552 Introduction to Computer Architecture Spring 2010 Section 1
Instructor David A. Wood and T. A. Tony Nowatzki
URL: http://www.cs.wisc.edu/~david/courses/cs552/S10/

CS552 Class Project

Documents

Tools

(Add /p/course/cs552-david/public/html/S10/handouts/bins to your path to use these tools. )

Project Modules:

Basic Modules:
D-FlipFlop
Clock-Reset Module – (Updated 3/2/2010)

Top Level Processor Modules:
proc.v  -  Your Processor
proc_hier.v -  Your Processor with clk-rst module added.
proc_hier_bench.v – Testbench for Non-pipelined Processor
proc_hier_pbench.v -  Testbench for Pipelined Processor  (use wsrun.pl -pipe)

Memories:
Single Cycle Memory
Single Cycle Aligned Memory
Stalling Memory
Four Banked Memory

Cache Module

 
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