UW-Madison
Computer Sciences Dept.

CS/ECE 552 Introduction to Computer Architecture


Spring 2012 Section 1
Instructor David A. Wood and T. A. Ramkumar Ravikumar
URL: http://www.cs.wisc.edu/~david/courses/cs552/S12/

Notes on the interaction of stall and forwarding

Pipeline stalls can interact in subtle ways with data forwarding (aka bypassing). This note explains why the pipeline used in the book should handle stalls in decode.

Recall that without data forwarding, an instruction stalls in decode (D) if an earlier instruction produces its result and waits until the value is written to the register file. With data forwarding, it is tempting to stall the pipeline in the execute (X) stage until the value is available. However, while there are many different pipeline designs that do stall in execute, that won't work for this pipeline. Consider the following code sequence:

                  1  2  3  4  5  6  7  8
add $1, $2, $3    F  D  X  M  W
lw  $2, 0($1)        F  D  X  M  W
or  $3, $1, $2          F  D  X  X  M  W
                           ^ or instruction reads old values of $1 and $2
                              ^ or stalls in execute to wait for load value
                                 ^ $1 has already been written, or gets old value

Note that neither input to the or instruction is available during decode (cycle 4). Furthermore, the or instruction must stall on the lw instruction, since the load value won't be available until cycle 6. However, by cycle 6, the value produced by the add has already been written to the register file ($1) and is no longer available to be bypassed.

There are several solutions to this problem, but the simplest for this pipeline is to move the stall back to decode and allow register file bypassing (which is, in fact, what the book says to do).

Consider the execution in this case:

                  1  2  3  4  5  6  7  8
add $1, $2, $3    F  D  X  M  W
lw  $2, 0($1)        F  D  X  M  W
or  $3, $1, $2          F  D  D  X  M  W
                           ^ or stalls in decode
                              ^ bypass new $1 value to DX latch
                                 ^ bypass load value from MW latch to ALU

By stalling in decode (cycle 4), when the add writes back its value to $1 (cycle 5), we can also bypass the register file and save this new value in DX pipeline latch. Then in execute (cycle 6) we can bypass the load value ($2) to the ALU in time to execute the or instruction.

 
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