CS 552 Spring 2012

CS/ECE 552 Introduction to Computer Architecture

Spring 2012 Section 1
Instructor David A. Wood and T. A. Ramkumar Ravikumar
URL: http://www.cs.wisc.edu/~david/courses/cs552/S12/

Four Banked Memory

Four Banked Memory is a better representation of a modern memory system. It breaks the memory into multiple banks. The four-cycle, four-banked memory is broken into two Verilog modules.

Copy final_memory.syn.v in the same directory as final_memory.v


                        +-------------------+
                        |                   |
      Addr[15:0] >------|   four_bank_mem   |
    DataIn[15:0] >------|                   |
              wr >------|    64KB           |-----> DataOut[15:0]
              rd >------|                   |-----> stall
                        |                   |-----> Busy[3:0]
             clk >------|                   |-----> err
             rst >------|                   |
      createdump >------|                   |
                        +-------------------+

Timing:

    |            |            |            |            |            |
    | addr       | addr etc   | read data  |            | new addr   |
    | data_in    | OK to any  | available  |            | etc. is    |
    | wr, rd     |*diffferent*|            |            | OK to      |
    | enable     | bank       |            |            | *same*     |
    |            |            |            |            | bank       |
                  <----bank busy; any new request to--->
                       the *same* bank will stall

This figure shows the external interface to the module. Each signal is described in the table.

Signal	In/Out	Width	Description
Addr	In	16	Provides the address to perform an operation on.
DataIn	In	16	Data to be used on a write.
wr	In	1	When wr="1", the data on DataIn will be written to Mem[Addr] four cycles after wr is asserted.
data_in	In	1	When rd="1", the DataOut will show the value of Mem[Addr] two cycles after rd is asserted.
clk	In	1	Clock signal; rising edge active.
rst	In	1	Reset signal. When "rst"=1, the memory will load the data from the file "loadfile".
createdump	In	1	Write contents of memory to file. Each bank will be written to a different file, named dumpfile_[0-3]. Active on rising edge.
DataOut	Out	16	Two cycles after rd="1", the data at Mem[Addr] will be shown here.
stall	Out	1	Is set to high when the operation requested at the input cannot be completed because the required bank is busy.
Busy	Out	4	Shows the current status of each bank. High means the bank cannot be accessed.
err	Out	1	The error signal is raised on an unaligned access.

This is a byte-aligned, word-addressable 16-bit wide 64K-word memory.

Requests may be presented every cycle. They will be directed to one of the four banks depending on the least significant 2 bits of the address.

Two requests to the same bank which are closer than cycles N and N+4 will result in the second request not happening, and a "stall" output being generated.

Busy output reflects the current status of each individual bank.

Concurrent read and write not allowed.

On reset, memory loads from file "loadfile_0.img", "loadfile_1.img", "loadfile_2.img", and "loadfile_3.img". Each file supplies every fourth word. (The latest version of the assembler generates these four files.)

 Format of each file:
     @0 
     <hex data 0>
     <hex data 1>
     ...etc

If input "create_dump" is true on rising clock, contents of memory will be dumped to file "dumpfile_0", "dumpfile_1", etc. Each file will be a dump from location 0 up through the highest location modified by a write in that bank.

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