CS/ECE 552 Introduction to Computer Architecture Spring 2012 Section 1 Instructor David A. Wood and T. A. Ramkumar Ravikumar URL: http://www.cs.wisc.edu/~david/courses/cs552/S12/

Project

Project Deadlines
Project Team information due	February 24
Test Plan due	February 29
Design Overview due	March 14
Project Demo I	March 23
Project Demo II	April 23
Project Demo III	May 11

Summary

The CS 552 term project is the complete functional design of a microprocessor called the WISC-SP12. All components of your design will be written in Verilog. As with the course homeworks, the CS 552 Verilog restrictions apply, and all final code is expected to pass the Vcheck program.

The project will be completed in groups of two or three. These groups should be formed no later than February 24th. Email me and the TA the group members and a unique team name. Your email should have the subject line: CS552 group creation.

The specifics of the WISC-SP12 architecture are found in two separate documents, each found in the project section of the course web page. The first describes the microarchitecture, including register file specifications, memory system organization, etc. The second document outlines the WISC-SP12 ISA.

The project will progress in several distinct stages. Some of these stages are enforced through grading deadlines; others are not. See the Project Deadlines and Grading and Project Stages sections for more specific details.

Each stage of the design makes the processor progressively more complicated. For your own benefit, it is strongly recommended that you not proceed to a new stage before you are confident the current stage is working to specification. Debugging errors in a complex design can quickly diminish your level of enjoyment during the project.

Many of the Verilog problems in the homework assignments were designed to be compatible with the project. Please feel free to reuse these modules (of course, fixing any errors first!).

In addition to the previous homework problems, you will be provided with several reusable modules that you can use in your design. Most of these are Verilog implementations of memory system components. Please note that these files do not follow the CS 552 Verilog restrictions, so don't include them when you run Vcheck. A complete listing of the modules, along with detailed descriptions of their use, can be found in the Project modules provided page.

An assembler for the WISC-SP12 ISA is provided for your use. Sample test programs are also provided, although you are strongly encouraged to write custom tests to augment these. Be aware that these test programs were written for a slightly different ISA specification and therefore may not work as advertised. It will be your job as diligent designers to determine if unexpected behavior occurs due to a bug in your design or as the result of the change in ISA.

IMPORTANT NOTES

• Start early: This project is designed to take a considerable amount of time.
• Plan ahead: You may find that the instructor and TA will be very inaccessible the night before a deadline.
• Ask questions: If you are getting stuck on some problem ask for help. Ask me, the TA, or your classmates.
• Functionality: Getting a working design is of paramount importance. Optimizations, clock-speek and bonus questions come 2nd. First make sure your design works!

If you finish really early, you will get the opportunity to possibly map your design (or a part of it) to an FPGA chip.

If you are able to complete this project without the unnecessary stress that procrastination imposes, it is our belief that you will find this to be a highly rewarding experience.

Document preparation resources

• Latex
• openoffice draw - my preferred drawing tool
• Xfig - for drawing figures. /s/std/bin/xfig
• jgraph - for drawing graphs. /unsup/jgraph
• Generating eps/ps files using Excel. Scroll down to where it says "Plot bar chart (filled boxes)".

Presentation and writing resources