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Stalling Memory
After
you have successfully made a pipelined version of your processor, the
next step will be to make your design capable of handling arbitrary
stalls in the memory accesses. To do this, replace your single-cycle
memory modules with these "stalling memory"
modules. verilog
source, synthesizable
version.
This module has an interface identical to the cache interface in mem_system_hier.v. With the same semantics.
Copy
the synthesizable version in the same directory as the stallmem.v
file.
Examining
the source file stallmem.v, you will see "rand_pat", a
linear feedback shift register which controls the "ready"
output. This is a 32-bit number. You can change its initial value by
specifying the seed used for random number of generation. You can do
this by passing in "-seed" to wsrun.pl. For example:
wsrun.pl -seed 45 -prog foo.asm proc_hier_pbench *.v
If
you are executing from inside ModelSim with run -All or using a
testbench of your own for preliminary testing, you can pass in the
seed, by adding the string "+seed=<value>" to the
vsim command. Or simply edit stallmem.v and set the seed to a
different value.
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