CS/ECE 552 Introduction to Computer Architecture Spring 2012 Section 1 Instructor David A. Wood and T. A. Ramkumar Ravikumar URL: http://www.cs.wisc.edu/~david/courses/cs552/S12/

WISC-SP12 MicroArchitecture Specification

The WISC-SP12 architecture that you will design for the final project shares many resemblances to the MIPS R2000 described in the text. The major differences are a smaller instruction set and 16-bit words for the WISC-SP12. Similarities include a load/store architecture and three fixed-length instruction formats.

1.  Registers

There are eight user registers, R₀-R₇. Unlike the MIPS R2000, R₀ is not always zero. Register R₇ is used as the link register for JAL or JALR instructions. The program counter is separate from the user register file. A special register named EPC is used to save the current PC upon an exception or interrupt invocation.

2.  Memory System

The WISC-SP12 is a Harvard architecture, meaning instructions and data are located in different physical memories. It is byte-addressable, word aligned (where a word is 16 bits long), and big-endian. The final version of the WISC-SP12 will include a multi-cycle memory and level-1 cache. However, initial versions of the machine will contain a single cycle memory. See the project deadlines for more details.

The WISC-SP12 cache replacement policy is deterministic. See the cache module description for an outline of the algorithm you must use.

3.  Pipeline

The final version of the WISC-SP12 contains a five stage pipeline identical to the MIPS R2000. The stages are:

1. Instruction Fetch (IF)

2. Instruction Decode/Register Fetch (ID)

3. Execute/Address Calculation (EX)

4. Memory Access (MEM)

5. Write Back (WB)

See Figure 4.41 on page 355 of cod4e for a good starting point.

4.  Optimizations

Your goal in optimizations is to reduce the CPI of the processor or the total cycles taken to execute a program. While the primary concern of the WISC-SP12 is correct functionality, the architecture must still have a reasonable clock period. Therefore, you may not have more than one of the following in series during any stage:

• register file

• memory or cache

• 16-bit full adder

• barrel shifter

You may implement any type of optimization to reduce the CPI. The required optimizations are:

• There are two register forwarding paths in the WISC-SP12; one within the ID stage and between the beginning of MEM and the beginning of EX.

• All branches should be predicted not-taken. This means that the pipeline should continue to execute sequentially until the branch resolves, and then squash instructions after the branch if the branch was actually taken.

5.  Extra Credit: Exceptions

Exception handling is extra credit. If you choose not to implement exception handling, an illegal instruction should be treated as a nop.

IllegalOp is the only defined exception in the WISC-SP12 architecture. It is invoked when the opcode of the currently executing instruction is not a recognized member of the ISA. Upon finding an illegal opcode, the computer shall save the current PC into the reserved register EPC and then load address 0x02, which is the location of the IllegalOp exception handler. Note that if you choose to implement exceptions, address 0x00 must be a jump to the start of the main program.

The exception handler itself need not be complex. At a minimum it should load the value 0xBADD into R₇ and then call the RTI instruction.

6.  Extra Credit: Branch Target Buffer

A branch target buffer (BTB) is a simple structure which caches the locations of previous branches. When a branch is predicted as taken, the Branch Target Buffer can be used to guess the location to jump to. This should allow correctly predicted branches to flow through the pipeline without creating stalls. You may follow the basic model used on page 122-124 of the H&P Book (Computer Architecture a Quantitative Approach) for your design, although there may be some modifications required. Your implementation must be direct mapped and have 16 entries, and (for simplicity) you should predict taken on every branch.