CS/ECE 755: VLSI Systems Design

Spring 2002 Offering

Instructor:

Prof. David Wood

david@cs.wisc.edu

TA:

Pranay Koka

pkoka@cs.wisc.edu

What's New in Class

First lecture will be Wednesday, January 23rd.
Friday, January 25th will be a discussion section on the tools led by Pranay.

Course Information

Course times: MWF 11:00am--12:15pm
Lecture room: 3534 Engineering
Midterm Exam: Wednesday, March 20th, in class
Final Exam: Friday, 2:45pm, May 17th, 2002
Room 1263 Computer Sciences

Course Goals

Introduce students to trade-offs in modern MOS technologies, and their impact on computer architecture and microarchitecture.
Introduce students to the CAD tools needed to manage the complexity of VLSI designs.
Get a feel for the types of chips to be designed in the next century.

Course Contents:

In this course we will study the design of digital systems using MOS circuits, with an emphasis on architectural and micro-architectural trade-offs. We will treat the subject as a natural outgrowth of digitial system architecture, and will not assume any background in semiconductor devices. This course will have a different emphasis than when it is taught by the ECE faculty. When taught in ECE, the course emphasizes circuit design, circuit optimization, and CAD algorithms. In this course, we will touch on each of these areas, but spend more time focusing on the architectural aspects of VLSI systems design. We will examine the impact of VLSI technology on contemporary processor and memory system designs.

This is NOT a circuits course

CAD Tools and Computers:

We will be using the Mentor Graphics CAD tools. These are extremely powerful commercial tools. However, they have a "large learning curve," and we anticipate some problems. Students should take this into account when starting individual assignments and their project. There will be considerable leeway granted if there are widespread problems with the tools, however, failing to leave sufficient time before the due date is not a valid excuse. The computers assigned for the course are the color Suns in the Computer Sciences Instruction labs (e.g., Room 1358, 1368, and 1347/1349 CSS). If you are not familiar with UNIX, you should attend one of the UNIX orientation sessions given during the first two weeks of classes.

ECE students will also have accounts on the CAE machines. Most of the tools will be available at CAE, although there may be minor differences in the configurations. We will try to minimize these as much as possible.

Although the details of the design tools will not be covered in class, the TA will organize several additional recitation sections to help you learn them.

Course Requirements:

Exams:There will be both a midterm exam and a final exam. The midterm will cover all material upto the exam. Both exams will cover all the material in the text, lectures, and assigned readings. Both will be two hour exams held outside of class hours.
Homework: There will be 4-5 assignments in the first half of the semester. These assignments are geared towards introducing you to the design tools and technology as well as making sure you know the material. Assignments will not be weighted equally; the approximate weight of each assignment will be specified when it is handed out. Assignments are due at the end of class; however, you are expected to be in lecture, on time, when homework is due. Failure to complete homework assignments can have a significant negative impact on your grade. Except when explicitly stated otherwise, all assignments must be done individually. You are encouraged to discuss the assignments with your peers, but YOU MUST WRITE UP YOUR ASSIGNMENT INDIVIDUALLY AND IN YOUR OWN WORDS.
Project: During the second half of the course, you will work in groups of 2-4 students to design, layout, and simulate a project. You are free to choose your own group, subject to instructor approval. If possible, your group should contain at least one CS student and one EE student. I will give you a handout describing the overall project design. You will be responsible for the detailed design decisions, implementation, and simulation. Alternatively, you can pick your own project, subject to instructor approval. Past experience indicates that the project will be very time consuming, but also very rewarding. Students should also be aware that the tools may have some bugs (or simply just be hard to learn how to use correctly). We will do everything we can to minimize the inconvienences, but students should plan to leave time for unanticipated problems.
Presentation: The last week of lectures will be used for in-class project presentations.

Course Grading:

Homework	20%
Project	35%
Midterm	20%
Final	25%

Tentative Schedule:

Week	Dates	Topics (Approximate)
1	1/23-1/25	Overview, MOS as an Abstract Technology, CAD
2	1/28-2/1	MOS Transistors and Gates, Delay Estimation
3	2/4-2/8	Simulation, Processing
4	2/11-2/15	Topology, PLAs, Catchup
5	2/18-2/22	Sequential logic, Datapaths
6	2/25-3/1	Arithmetic, Testing
7	3/4-3/8	Review, Midterm
-	3/11-3/15	Spring Break
8	3/18-3/22	Processors
9	3/25-3/29	Processors
10	4/1-4/5	Memory Designs
11	4/8-4/12	Memory Designs
12	4/15-4/19	Billion Transistor Chips
13	4/22-4/26	Low Power Design
14	4/29-5/3	Review
15	5/6-5/10	Project Presentations
-	5/17	Final Exam, 2:45pm

Text and Reader

Principles of CMOS VLSI Design -- A Systems Perspective, Neil H. E. Weste and Kamran Eshraghian, 2nd Edition, Addison-Wesley, 1993 ISBN No. 0-201-53376-6
DRAFT Course reader (on-line) This will eventually be a collection of 10-15 papers.

Lecture Notes

Homeworks

Homework 0: assignment & answer
Homework 1: assignment & solution
Homework 2: assignment & Solution
Homework 3: assignment
Homework 4: assignment

Project

Spring 2002 Project

Preliminary Project Description

General project information

Projects from prior years

Spring 2001 project description
Reference for Spring 2001 project:
Timestamp Snooping: Building an Asynchronous SMP, Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. In the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.
ASPLOS presentation
Spring 2000 Course Project: Version Buffer
Spring 2000 Course Project Schedule
Spring 1999 project: VLSI design of a 4-port Crossbar Switch based on Virtual-Output-Queueing

Tutorials on CAD Tools

Spring 2002 tutorials:

Tutorial 0: Getting started
Tutorial 1: Custom layout using IC station
Tutorial 2: Hierarchial design using IC station
Tutorial 3: Design and layout using Standard cells
Tutorial 4: Diffusion sharing and transistor folding
Tutorial 5: Placing IO pads

Spring 2001 tutorials:

Beginning Tutorials

Creating Automatic Generated Layout from a HDL file

Creating a HDL file and simulating it using Modelsim
Sythesizing your design in Leonardo
Creating Automatic Generated Layout and Post Layout Simulations (incomplete)

Creating Automatic Generated Layout from a Schematic

Creating Full-custom Layout

Using ICstation to create full-custom layout

Miscellaneous

Options for Controlling the Placement of Ports while using Standard Cell Layout

Spring 2000 tutorials:

Tutorial 0: Getting Started
Tutorial 1: Design Architect
Tutorial 2: Quicksim II
Tutorial 3: Automatic Layout
Tutorial 4: Full-custom Layout
Tutorial 5: Creating and Simulating CMOS Designs
Tutorial 6: Simulating Full-custom Designs

Spring 1999 tutorials:

Tutorial 0: Getting Started
Tutorial 1: Using Design Manager
Tutorial 2: Logic Design and Simulation using the scn08hp Library of Standard Cells
Tutorial 3: Full-Custom Layout Editing with IC Station
Tutorial 4: Standard-Cells Layout Editing with IC Station
Tutorial 5: CMOS Circuit Design and Accusim Simulations
Tutorial 6: Netlist Extraction from Layout and Accusim Simulations
Tutorial 7: Using the MOSIS Design Kit for Schematic Driven Layout (by David M.Zar)
Tutorial 8: Automatic Placement and Routing of Hierarchical Layout Blocks

Supporting Material for the CAD Tools

Mentor ADK ASIC Design Kit 2.0 User Guide ( PDF or HTML)
ADK Tutorials
ADK Data Book 0.5
In order to use the on-line Mentor help, run mgc_acro.
MOSIS SCMOS_SUBM Design Rules v8.0: HTML Format.
Parametric test data for the AMI C5N process
A force file for Quickcim can be found here.
The timing characterization of the 2-input XOR gate from the scn08hp library of standard cells.
The SPICE-3 models for the nMOS and pMOS transistors of the scn08hp technology.
The sdl_prep script for creating an Accusim viewpoint for a circuit designed with the SDL-library transistors.
The dsim_prep script for creating a QuickSim viewpoint for a circuit designed with the SDL-library transistors.
A force file for Accusim can be found here.
Two-level logic minimization with Espresso (Man pages: espresso.1 and espresso.5). Here is an example of an input file for Espresso, specifying the truth table for a 2-bit adder. If you run espresso -o eqntott on this input file, you will get the three minimized logic equations, that you can easily implement using standard cells.
Mealy finite-state-machine design with MEG (Man page: meg.1). Here is an example of an input file for MEG, specifying the state machine for a multibus controller. If you run meg -t on this input file, you will get the truth-table for the next-state and output bits,, that you can then feed into espresso in order to get the minimized state-transition and output equations, that you can easily implement using standard cells.

Discussion Sessions

Spring 2001's discussions:

Discussion 1 (Feb 5) (.pdf file)
Discussion 2 (Feb 12) (.html file)

Spring 2000's discussions:

Spring 1999's discussions:

Discussion 1: (Feb-15, 1999) The overall toolset picture, some layout examples, and the standard-cells methodology.
Discussion 2: (Feb-22, 1999) More on Placement, Routing, Backannotation. Circuit Simulations with Accusim..
Discussion 3: (Mar-1, 1999) More on Full-Custom Layout Editing, Hierarchical Layout, IC Extraction..
Discussion 4: (Mar-15, 1999) More on LVS, and Schematic-Driven-Layout..
Discussion 5: (Mar-22, 1999) Three processor implementations: MIPS R10000, DEC 21164, HP PA8000.
Discussion 6: (Apr-5, 1999) The evolution of Alphas, and a PowerPC with copper interconnects.
Discussion 7: (Apr-14, 1999) A Sum-Addressed-Memory-Cache, and a Fully Parallel CAM.
Discussion 8: (Apr-21, 1999) Inside the Rambus Interface .