CS/ECE 755: Discussion Session II

Agenda for today:

  1. Finish Automatic Layout (options)

  2. Begin Custom Layout

Cell Placement

IC Station Reference Manual: (run mgc_acroread)

(also chapter 4 of IC Station User Manual)

Floor-plan

Cell Placement

Initial:

Initial and Improve:

Random and Improve:

Resume:

Port Placement

Routing

Two methods:
  1. Over-the-Cell-Router (OCR)
  2. Channel Router

Routing Steps:

Routing Options:

  1. Initial and Improve Global Iterations:

    Number of iterations for global routing. The router minimizes the layout area by rerouting nets in congested areas.

  2. Feedthru Cost:

    The OCR router can either insert an external feedthru between cells, or an internal feedthru over the cell. A lower cost makes external feedthru more likely.

  3. Primary Routing Layer:

    When it is based on the channel direction, Metal-2 is used for vertical channels and Metal-1 for horizontal channels.

  4. Extra Tracks:

    Number of extra track spaces to leave in each channel. This space can be used for manual editing.

  5. Expand Channels:

    Specify whether router is allowed to change size of channel areas.

Expert Routing Options:

  1. Channel Over Cell Routing:

    Specify whether any routing space inside a cell should be used for channel routing.

  2. Capacity-Driven-Layout:

    Specify whether the routing decisions should be based on minimizing the capacitance of interconnections.

  3. Taper Power:

    Specify whether the VDD/GND lines should be `tapered' during routing.

  4. Connect Block Power:

    Specify whether VDD/GND connections should be made on all blocks.

  5. Create Power Grid:

    Specify whether a grid of VDD/GDD lines should be created in all channels (when routing blocks).

  6. Align Mode:

    Specify alignment of layout blocks when routing is done.

Over-the-Cell-Routing (OCR) Options:

  1. Routing Levels:

    The routing layers that will be used. The first layer specified is the least preferred.

  2. Operation Mode Type:

    Specify whether routing should be done near the edges or the center of the channels.

  3. Restricted Levels:

    It is possible to specify the Poly layer here, for initial route segments directly from the gate of transistors.

  4. Work Factor:

    Determines the number of iterations of the algorithm.

  5. Maximum number of Bends and Vias:

    The bends refer to the same routing layer, while the vias refer to adjacent routing layers.

Custom Layout

Tutorial 4 - custom layout of an inverter

Steps:

  1. Identify circuit!

  2. Printout design rules (from class web page)

  3. Obeying design rules, draw rectangles representing ALL components/layers of the transistor

    (ie. poly, wells, metal1, metal2...).

    For example:

    ...and so on...

THE TRICK IS TO KEEP IN MIND THE GLOBAL PLAN WHILE OBEYING LOCAL RULES.

Read Adam Butts' "Layout Tips and Techniques" (off web page).