See
IEEE Journal of Solid-State Circuits, November 1998
Die Phote (15.25 by 15.25 mm)
Block Diagram of a Block
Match-Line Power for NOR and NAND Architectures
NAND match chains: a) one word, b) four words, c) core cell
Voltage (at 125C) of the active compare line in the model column at the top of the block with and without a sense amplifier
Search Control-Signal Generation
Simulated Search Waveforms
Read/Write Control-Signal Generation
Cascade Management Logic: a) Typical cascade configuration b) On-board cascade management circuits
Shmoo plot showing voltage versus search cycle times. The "x"'s show passing regions. All numbers are measured at 25C.
Waveforms showing the system clock HIT and two bits of the SA bus. The clock period is 100ns.
