CS/ECE 755-1, Spring 2002

Homework 1

due Friday February 1, in class

Approximate weight: 1%

Problem 1: (5 points)

Design a single complementary CMOS gate that implements the following function:

F = not ( (A . B) + (B . C) + (A . C)) where "." and "+" are the boolean AND and OR operators.

Problem 2: (10 points)

Use a combination of complementary CMOS gates to implement odd parity on eight input bits D<7:0>. Odd parity is defined to be one iff there are an EVEN number of ones in the data field D<7:0>.

Problem 3: (10 points)

Design a 2:4 decoder. The input S<1:0> is a binary number that indicates which of the four output signals O<3:0> should be one. Exactly one output should be a one and all others should be 0.

a) Design this decoder using complementary CMOS gates:

b) Design this decoder using switch logic. You may use inverters to invert the inputs. Be sure to observe the rules about which transistors pass 1's/0's well.