CS/ECE 755: VLSI System Design

Prof. David A. Wood

HOMEWORK #3

Due Friday, March 15, at end of class
Approximate Weight: 5%

Problem 1 (100 points):

To get you familiar w/ the different tools in the mentor toolset you will be designing a 16 entry 8-bit FIFO queue. This assignment focuses on the full-custom layout implementation. In the next assignment you will implement the same logic in standard cells.

Design Specification

Inputs: a Read signal, a Write signal, an 8-bit Data-In signal, and two clock signals Phi1 and Phi2 that implement a two-phase non-overlapping clock. All inputs are sampled on Phi1.
Outputs: a Full signal, an Empty signal, and an 8-bit Data-Out signal. All outputs are latched on Phi2 (so that they can be sampled on the following Phi1).
Behaviour: your circuit should implement the behaviour described in this C language-level specification.

There are a number of different approaches to implementing this FIFO. Adam Butts discussed one approach last week. There are alternatives, such as using a pair of shift registers to indicate the position of the head and tail entries (and never moving data).

In any case, you will want to use good hierarchical design (see Spring 2002 Tutorial 2). For example, the data portion of the FIFO should be constructed something like this.

design a 1-bit register cell
compose 8 1-bit register cells into an 8-bit register cell
compose 16 8-bit register cells into a 16 entry by 8-bit register file

Before you start any layout, think through your floorplan. How many wiring tracks will you need? What layers will be used for control and data? Do you need to leave space to buffer signals? How will power and ground be distributed? Can you reduce the area by sharing power and ground in neighboring cells?

Tools

Use IC station to design your FIFO in full-custom layout (see Spring 2002 Tutorial 1):
Make sure that each of your cells pass all the DRC tests.
Extract the netlist of the top-level layout cell and simulate it with Accusim (see Spring 2002 "Creating automatic generated layout and Post layout simulations"). Use the `lumped parasitic models' for both the interconnection capacitance and resistance. Make sure that the Accusim simulations verify the correctness of your design. Measure the delay and the rise/fall times of each of the adder outputs in the case of the worst-case delay excitation. Present the measured results in a tabular format.

Deliverables

Printout of the circuit design schematic.

Printout of AccuSim simulation traces (note: you do not have to include dozens of traces in your report; identify a few interesting cases -- ie. critical path excitation -- and include annotated traces only for them). Include one set of traces for the pre-layout simulations, and one for the post-layout simulations, if these two are significantly different.
A short summary of your design methodology, measurements, and conclusions. For example, you can report the resulting cell area for each option that you experimented with.
There will be another short (5 minutes or so) demo of the layout in one of the nova labs. Details TBA.
Note: You do not have to print the layout cells. That's why we have the demo.