CS/ECE 755: VLSI System Design

Prof. David A. Wood

HOMEWORK #4

Due Friday, April 5th, at end of class
Approximate Weight: 3%

Problem 1 (75 points):

To get you familiar with standard cell design, you will reimplement the design in Homework #3 with standard cells.

Tools

  1. Implement the logic design of the FIFO using da and the library of standard cells (as described in discussion session). Try to use composite gates (AOIs, OAIs, etc), since the standard cells that implement these gates are faster than combinations of standard cells that implement more primitive gates.
  2. Simulate your FIFO using quicksim in the nominal delay timing mode (as described in the Spring 2000 Tutorial 2 and Spring2001 tutorial 3). After you make sure that the design is correct, identify the critical path and the input transitions that `excite' that path. Based on this analysis, measure the worst-case delay of your FIFO.
  3. Generate the layout of the design using ic and the library of standard cells (as described in the Spring 2001 Tutorial 3 "Creating automatic generated layout and post layout simulations"). The `cell' (i.e., layout component) should be a square (or close to a square). The location of the ports should be as follows: the single bit signals (ie. Read, Write, Clock, Full, Empty) should be located on the top of the cell; the Data-In signals should enter the left side of the cell and the Data-Out signals should exit from the right side of the cell.


    4. Experiment with different floorplanning, placement, and routing options, until you get the most compact layout. Run DRC (Design-Rule Checking), and LVS (Layout-Versus-Schematic) checks, in order to make sure that the layout is correct and without any missing connections.

  4. Run post-layout simulations with quicksim, using a `backannotated' design viewpoint (as described in  Spring 2001 Tutorial 3 same as the one used for layout).

Deliverables

  1. Printout of the logic design schematic.
  2. Printout of QuickSim simulation traces showing critical path excitation pre- and post-layout.
  3. A short summary of your design methodology, measurements, and conclusions. Include cell areas for each placement/routing options that you experimented with and describe how you determined the critical path and the worst-case delay.
  4. There will be a short (5 minutes or so) demo of the layout at the nova lab. Details TBA.