CS/ECE 755 Spring 2002 Reader: DRAFT

Prof. David Wood

  1. ITRS Technology Roadmap for Semiconductors, Executive Summary (2001 Update)

  2. High-Performance Microprocessor Design, Paul E. Gronowski, Member, IEEE, William J. Bowhill, Member, IEEE, Ronald P. Preston, Member, IEEE, Michael K. Gowan, and Randy L. Allmon, Associate Member, IEEE, J. of Solid State Circuits, May 1999, Page 676.

  3. A 0.2-um, 1.8-V, SOI, 550-MHz, 64-b PowerPC Microprocessor with Copper Interconnects, Anthony G. Aipperspach, David H. Allen, Dennis T. Cox, Nghia V. Phan, and Salvatore N. Storino, J. of Solid State Circuits, Nov. 1999, Page 1430.

  4. A 1.6-GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme, Satoru Takase and Natsuki Kushiyama, J. of Solid State Circuits, Nov. 1999, Page 1600.

  5. Diefendorff, Keith. "Power4 Focuses on Memory Bandwidth", Microprocessor Report 13(13), Oct. 6, 1999.

  6. "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency" Raymond Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, and Joe Petolino, J. of Solid State Circuits, Nov. 1998, Page 1682.

  7. Shafai, Farhad et al., 1998, "Fully Parallel 30-MHz, 2.5 Mb CAM," IEEE Journal of Solid State Circuits, 33(11): 1690-1696, Nov. 1998

  8. Heald, Raymond, et al., "A Third-generation SPARC V9 64-b Microprocessor", IEEE Journal of Solid State Circuits, 35(11): 1526-1538, Nov. 2000