Viewpoints
Before we begin simulation we have to do a little setup: recall that
in the first tutorial we left the "technology" property empty (which
resulted in some warnings when we checked the schematic). Doing so
allows for a layer of abstraction between the schematic and the
simulation tool: namely, the same schematic can be used for multiple
delay models as well as multiple simulation tools. For instance the
standard library we're using can simulate three different delay
condition models under Quicksim II: nominal (when "technology"
is set to "scn08hp_nom"), worst case ("scn08hp_slow") and
best case ("scn08hp_fast").
Attaching delay properties to a schematic is done by creating a
"viewpoint". The easiest way to do this is with a script we've
provided (~cs755-1/public/html/mentor/qsim_prep) which makes calls to a tool called the
Design View Editor. Currently the script always sets the
technology parameter to "scn08hp_nom" and always calls the viewpoint
it creates "qsim.vp".
To create a viewpoint for the mux21 component I created in
~/cs755/mux21 for tutorial 1, I would do the following:
cd ~/cs755
~cs755-1/public/html/mentor/qsim_prep mux21
This would create a directory called qsim.vp inside the mux21
directory.
(Alternatively you could use a GUI version of the tool, by typing
dve, and following these instructions,
but I think you'll find it just gets in the way.)
Unit Delay Simulation
After you've created the quicksim viewpoint you are ready to simulate
your design. Invoke Quicksim II by entering the
mux21 directory and typing at the command prompt.
The following steps will guide you through an analysis of your circuit.
- First, open your design sheet. Use the OPEN SHEET
icon on the palette to do this. You may want to re-size the schematic
window to make things more easily visible.
- Next, you need to specify the input signals. Mentor calls
this a force. You need to specify which signal is to be
``forced.'' You do this by selecting the signal in the schematic, the
same way you would in Design Architect. Select the A
port in the schematic.
- Now, select the STIMULUS button at the top of the
palette. The stimulus palette is now displayed.
- Next, select the ADD FORCE icon to add the forces to
the selected signal. A dialog box will appear. Note how the selected
signal is the name in the dialog box.
- The box lets you enter time-value pairs. As you enter one
pair, the dialog box expands to let you enter more pairs. DO NOT use
the Enter key between fields; use the Tab key.
Enter accepts the values in the dialog box and closes it.
Let's enter the following value pairs: (0,0), (1,10), (0,20), (1,30),
(0,40). Your screen should now look something like this.
- Click on OK or type Enter to dismiss the dialog
box. If the button is out of the box, you can "slide" the mouse
cursor down to the bottom edge to cause it to scroll up into view.
- Now unselect the input signal A and select signal
B. Use the same procedure to enter the following values:
(1,0), (0,10), (1,20), (0,30), (1,40).
- Do the same thing for signal SEL using these values:
(0,0), (1,25), (0,40). It is important to note that if you want to
change any of these stimuli after you have run the simulation, you
must reset simulation state. One way to do this is by clicking on the
RESET ... icon in the palette (see step 1. below).
Force events which occur prior to the current simulation time will not
be added. So if you run the simulation 200nS then try to add forces
at 150nS, they will be ignored. When you reset simulation state, your
current simulation time goes back to 0nS.
- Now that you have set up the input stimuli, you are ready to
set up your simulation output. The output is placed into a trace or
list window. The trace window looks like a logic analyzer, and the
list window reads more like a logic table. We'll use both to verify
the correctness of our design. In general, however, you may pick
whichever method you prefer for a given design. First, select all of
the inputs and outputs by clicking on their corresponding wires in the
schematic window.
- Next, put them in a trace window by pressing the TRACE
button on the palette.
- Open a list window by pressing the LIST button.
- If you want to add signals to either window, select them in
your schematic and then press the appropriate palette button. To
remove signals, select the signal and press the delete key on
the keyboard.
- If you cannot see all of the signals in either the trace or
list windows, resize them so you can see them all.
- Unselect all signals with the F2 Function key.
- Now let's run the simulation for 50 ns. To do this, simply
type ``run 50''(the default time scale is set to nanoseconds).
A prompt bar appears whenever you start typing in the QuickSim window.
Hit the enter key to execute the command in the prompt bar,
otherwise, if you do not want to execute a command this way, just hit
the esc key.
(NOTE: Force files provide a much more efficient means of
setting forces. The following file sets the forces to the same values
as the above steps: FORCES. To simulate using
this force file, copy it to a known location, select
Add->Forces->From file... from the menu bar, and type in the
path to the force file in the dialog box that pops up.)
The trace and list windows will show the results of the simulation
run. In the trace window, you can use the shift-F8 key to view
the entire simulation. In either window, you can scroll up/down and
left/right to view the time of interest. The trace window also allows
viewing a certain area by using the view area command from
the pop-up window in the trace window.
Now you can look at the trace and list windows and verify the correct
behavior of the 2-1 multiplexor. Remember, when the select line
(SEL) is low, the B input is gated to the output, and
when the select line is high, A goes to the output. Also note
the small spike at the output at about time 40 ns. Why does this
happen?
To understand what's going on, you need to understand a little about
how the simulator works. What you just did above was to run the
simulator in unit delay mode. What this means is that all
delay times for each gate are identical. In this case the common unit
delay is 0.1 ns. For the signal SEL to get to the output, it
must go through an inverter, an AND gate and then an OR gate. Hence,
it is delayed by 0.3 ns in the unit delay mode. Knowing this, we can
explain the reason for the spike.
At time 40 ns, we forced SEL low. This should select the
B input. B was forced high at 40 ns, also. At 40.1 ns,
B, the output of the inverter, is forced high due to the
unit delay through the inverter. Now the inputs to the lower AND gate
are both high so the output would be high also. This happens at 40.2
ns. This causes a high to appear at the OR gate so the output of the
OR gate goes high at 40.3 ns. At 40.2 ns, however, both inputs to the
OR gate were low, so the output went low for 0.1 ns. Can you show
that this is so?
Nominal Delay Simulation
Unit delay mode is often useful for testing basic functionality.
It does not do a good job of reflecting potential timing problems in
real hardware however, for obvious reasons. We shall now re-simulate
the mux using the nominal delays found in scn08hp cells.
- The first thing we need to do is reset the simulation. From
the top menu bar, enter Run->Reset, or click on RESET
... icon in the palette. A dialog box will appear. Select the
State button to reset the state of the simulation. Deselect
the Save `results' waveform DB box. Press the OK
button.
- Now we need to change the timing mode. To do this select
Setup->Kernel->Analysis from the top menu bar.
- In the dialog box that appears, select Delay and then
press the OK button.
- You must also tell the simulator to calculate the timing for
each gate. First, from the top menu select
Edit->Select->All->Instance to select all of the gates.
- Next, from the menu bar, select
Setup->Kernel->Change->Timing Mode. This is also available via
the TIMING MODE icon in the SETUP palette.
- In the dialog box that appears, press the Change
button and then click on ``typ'' on the full delays
line.
- Press OK to close the dialog box.
- Now that you are in delay mode, the specified delays will be
used. Type `` run 50'' to run the simulation, again.
Notice how, this time, there are much greater delays between input and
output events. The list window is very useful in determining the
delays. If you scroll to the top of the list window, you will notice
some ``Xr'' signals. This means that the signal is undefined
at this initial simulation time. Due to the delays in the circuit,
the output is not defined for 2.6 ns. This is the point where all
signals have propagated through to the output. If any input to a gate
is undefined, then it's output is also.
Another nice feature in the list window is that whenever a signal
changes value, it is highlighted. This makes it easy to see when
signals change.
Finding Delays in the Trace Window
Let's find the delays between some signals in the circuit and analyze
the circuit with these delays:
- Select the trace window.
- Press the WF EDITOR button on the palette.
- Now press the DELTAS icon. This brings up a prompt
bar and allows us to find the time difference between any two edges
very easily.
- Click the mouse near the first falling edge of B and
then of the first falling edge of OUT. This will show us
the delay from the input B to the output. The result is
shown in the message line at the bottom of the window. Notice how it
is 2.2 ns? The signal must propagate through two gates, and both
times the signal is falling, so the sum of the fall times is 2.2 ns.
- Press the escape key or click on Cancel on the prompt
bar to cancel the edge delta calculator.
This concludes your introduction to digital simulation using the
scn08hp library. To exit QuickSim II , simply close the
window. You will be prompted if you want to save anything. Respond
by selecting Without Saving and press OK.