FULL CUSTOM LAYOUT

Before starting, append the following command to your ~/mgc/startup/icgraph.startup:

$show_layer_palette(@replace, ["cell_inst_name", "N_WELL", "ACTIVE", "P_PLUS_SELECT", "N_PLUS_SELECT", "POLY", "CONTACT_TO_POLY", "CONTACT_TO_ACTIVE", "METAL1", "VIA", "METAL2"]); This adds a "layer pallete" to your ic window which you'll find can save lots of time...

Laying Out a Cell

This tutorial guides you step-by-step through the drawing of the layout of this inverter:

The gate of the PMOS will have a length of 2 lambdas (L=2) and a width of 17 lambdas (Wp=17). The gate of the NMOS transistor will have the same length but the width will be 13 lambdas (Wn=13).

Start IC Station, by typing ic at the command line.
Note: it is very important to see the right colors when drawing layout. Unfortunately, Netscape is a color-map hog, so if you have Netscape running, kill it before starting ic and then start it back up.
Select File->Process->Load from the menubar. In the resulting dialog box, type $MGC_HEP/technology/ic/scmos to specify the SCMOS process. Then, select File->Load Rules, and type $MGC_HEP/technology/ic/scmos.rules. This loads the corresponding set of Design Rules that we will use in this class.
Note: these Process and the Design Rules will be automatically loaded if you have the right startup file (icgraph.startup) in the mgc/startup directory.
Select Cell->Create to create a layout cell. In the form that will appear, give the Cell Name `my_inverter'. The Angle Mode has to be `Ninety'. This means that only horizontal/vertical lines and rectangles can be drawn. The other options need not be changed. Note that the No Connectivity mode is selected. This means that you are going to do full-custom layout (instead of standard-cells, for example). The form should look like this this.
From the menu on the right of the screen, select Easy Edit.
Select View->Zoom->ToGrid. The area of each square (formed by four dots) is a half-lambda squared.
First create the PMOS transistor. Since the length of the transistor will be 2 lambdas and the width 17 lambdas you need to add a poly rectangle with these dimensions. This will be the gate of the transistor. Select AddObjects->Shape. There are two ways to select the poly layer:
1. Click on the Options of the menu that will appear at the bottom. You see all the different layers listed . The color and pattern, a code number (GDS II format), and a short description appears for each layer. Notice the correspondence between the code numbers and the CIF names in table 4 of the handout MOSIS Scalable CMOS Design Rules. Scroll down and select Poly (code 46). Click OK at the above form.
  OR:
2. Click on the Poly button of your "layer pallete". (Told you it would save time...)
Draw a rectangle with length 2 (4 squares) and width 17 (34 squares). Unselect the poly rectangle by pressing F2. It should appear as a red shape now.
Now add a rectangle that corresponds to the Active region of the transistor (layer 43, CAA). From the design rule 3.4 you know that the active region has to extented by 3 lambdas in each side of the polysilicon. So draw a rectangle with dimensions 8 x 17 centered at the poly. The layout should look like this now.
See design rule 3.3: we have to extend the poly gate 2 more lambdas beyond the active at both ends. The extension can be made easily with the notch command. Select the poly layer (note that only the select layer has to be selected). Click on the notch command at the right of the screen and draw the extension of the poly layer. The layout should look like this now.
(Note: sometimes it is difficult to select just one shape. The Select->One command can come in handy in these cases. Also, note that at the top right hand side of the screen there is a `selection count' indicating the number of objects that you have selected.)
If we place a P+ select layer (layer 44, CSP) around the active region we have a PMOS transistor. See the design rules for the select layer (page 10). The select layer rectangle has to extend 2 lambdas beyond the active layer (rule 4.2). Draw it with dimensions: 10 x 19. (Actually, for this layout to be a PMOS transistor we also need to draw an N-well around the P+ select -- we'll add the N-well later). The layout should be now look like this.
We can create the NMOS transistor by copying the PMOS transistor. Select all your drawing. Then select Edit->Copy. Place the copy somewhere well below the PMOS transistor. Select the P+ select layer and delete it. Then replace it with an N+ select (layer 45, CSN) of the same dimensions.
The NMOS transistor should be 13 lamdas wide, so we have to reduce the dimensions of the poly, the active and the N+ select layers. Use the Notch command. A few words on this useful command (from the IC Station User's Manual, page 25-52): "If you select a polygon, you can notch-in and notch-out any edge, and the overall area of the polygon changes by the area of the notch that you create. When you notch in, you cut out parts of the selected shapes; when you notch out, you add to each selected object. You can also use "notch" to cut a hole in an object or you can notch through an object to create multiple objects."
Connect the two transistor gates together with a piece of poly. The layout should now look something like this.
We now have to connect the drains of the transistors together. The connection will be made using Metal 1 (layer49, CMF) and Contacts to Active (layer 48, CCA). See the design rules on pages 12, and 15. What is the correct sizing for each of the layers? Note that you have to extend the active and the select layers.
(Here and for the remainder of the tutorial you have to figure out the right dimensions based on the design rules. Remember: the goal is an area-efficient layout; use the smallest dimensions that do not violate the design rules.)
So, extend the active and the select layers of the two transistors. Place a contact to active on the active on the drain side (right-hand side) of the pmos. Remember that the more contacts you have the better the connection (less resistance), but also remember that contacts need to be placed at a minimum spacing of two lambdas. Copy the contact to the appropriate positions. Notice that for the pmos transistor you can place four contacts while for the nmos only three. Finally, draw a metal 1 rectangle that extends over both drains. The layout should now look like this.
Now draw the power distribution lines (VDD and GND). Use Metal 1. The width of the power distribution lines is usually larger than the minimum, to minimize resistance (the wider the line, the smaller its resistance). For this example, use a width of six. The layout should now look like this.
Now connect the source of the PMOS to the VDD line and the source of the NMOS to the GND line. Use metal 1 for the connections. The width of these lines can be the same as the width of the line that connects the drains (4 lambdas). Place the contact to active as you did before. The layout should now look like this.
As mentioned above, you still have to draw an N-well around the PMOS transistor. Notice the well has to be at least 5 lambdas far from the source/drain active (design rule 2.3). The layout should now look like this.
Now place the substrate contacts. This means connecting the N-well to VDD and the P-substrate to GND. For the N-well contact you need a N+ select square, an active square, and a contact. They can all have the minimum dimensions. Note that the contact and, if possible, the active, have to be below the metal 1 VDD line to improve the connection. Do the same for the P-substrate contact. In this case you need to have a P+ select square instead. The layout should now look like this.
Now create the input and output of your inverter, using metal 2 for these ports. Note that the output is the drains-connection which is in metal 1. So extend this metal 1 line to the right [you actually don't need to do this...] and draw a `via' square (layer 50, CVA) on top of it. See the design rules 8.1-5 for the right dimensioning. Then draw a Metal 2 (layer 51, CMS) square on top of the via and of the metal 1 layer. See the design rules 9.1-3. Finally draw one more layer on top: the metal2.port. Notice:
1. ports aren't on the pallete, you have to click on the options in the ADD SHAPE dialog box.
2. yes, it is difficult to distinguish metal ports from metal.
3. ports are logical objects, so they have no sizing constraints; make them as big or small as you like.
Select the port you just drew and then select Connectivity-> Port-> MakePort. In the dialog box that results, specify that it will be an Output Signal with name OUT. The layout should now look like this.
The input is a bit more complex. Since it is a poly connection of the two gates, you have to make a connection from poly to metal 1 and then a connection (via) from metal 1 to metal 2. Notice that the two connections cannot be one above the other. You have to extend the poly layer to the left, add a metal 1 rectangle, add a Poly contact (layer 47, CCP), add a metal 2 rectangle, and then a via. After you do the above, draw on top of the metal 2 rectangle a metal2.port rectangle, the same as you did for the output port. This time, you will specify that this will be an Input Signal port with name IN. The layout should now look like this.
Draw the VDD and GND ports using the same procedure. You will use metal1.port (layer 2). This time you will specify that the ports are Power Inputs with names VDD and GND respectively. This completes the port specification of your inverter. The final layout should look like this.
At this point you have to check your layout for any violations of the scmos technology design rules. At the right part of the screen, select Back, ICrules, and then Check. At the menu that will appear press OK. After the checking is complete you can see your layout "bugs" by clicking at "First" for the first error and then at "Next" for subsequent errors. The design rule that is being violated at each case appears at the bottom of the screen. You can return at the editing mode clicking on "Back" and then "EasyEdit". Correct any errors that exist in your layout.
If you have a layout design that is free of errors you are done. Note however that a correct layout is not necessarily a good layout. The following are characteristics of a good layout:
1. It is as small as possible (following, of course, any specifications of transistor lengths and widths, and widths of the power distribution lines).
2. Parasitics (capacitance and resistance) have been reduced as much as possible. For example, remember that active regions add to transistor capacitances, the poly layer is highly resistive, and the number of contacts at a connection should be large as possible to reduce the connection resistance.
3. An interface that allows easy connections w/ other components of the global layout.

Hierarchical Cells

In large designs, we normally follow a hierarchical layout approach (as opposed to a flat layout approach). Suppose, for example, that you want to design a buffer using two instances of the 1-bit inverter of the previous section, First, you need to do some additional editing on the 1-bit inverter, so that it is ready for hierarchical layout.

Start by adding a rectangle with the fp1 layer around your inverter. This layer does not correspond to a physical mask layer. It is only used for providing IC Station with information about the boundary of a cell. The cell should look like this.
Note that the fp1 outline may not have to entirely include the shapes of a cell. In this case, for example, we've left parts of the N-well beyond the cell boundaries, since there will be no design-rule violations if N-wells of different instances overlap with each other. In general, we want the cell to be as small as possible, while obeying the constraint that adjacent placement of arbitrary cells will not cause design-rule violations.
An important concept in hierarchical designs is that of a cell's aspect. The internal aspect of a cell is its complete implementation, with all the including shapes being visible. For example, the previous image shows the internal aspect of the inverter. The external aspect of a cell shows the interface abstraction of a cell, or in other words, what is visible from this cell at the higher-level of hierarchy. It is good practice to includeall the Metal-1 and Metal-2 shapes in the external aspect , so that the routing wires at the higher-levels of the hierarchy do not inadvertantly cross internal metal layers in the cell. For example, the external aspect of the inverter looks like: this.
To specify that certain shapes are in the external aspect only, or in both the external and in the internal aspects (as in this case), you have to either select them and then change their aspect with the menu Objects -> Change -> Aspect, or to draw them from the beginning in the correct aspect, setting the corresponding option in the Add Objects -> Shape menu. You can control the cell aspect that is visible at each time using the menu View -> Show -> Aspect.
Now create a cell from the layout of the 1-bit inverter. This cell can be either a block or a standard cell (or several other types of IC Station cells that we ignore for now). First, select all the shapes of the inverter layout. Then, select the menu Objects -> Make -> Cell . In the menu that will appear you have to select the type of the cell and a logical name for the cell. In this case, specify that the cell will be a block (which is what we will be doing in the rest if this course) and give for example the name inv_cell. Then, save the cell using the menu File -> Cell -> Save Cell -> Hierarchy and close it.
Now, create a full-custom cell for the buffer. The buffer will consist of two inverters connected in series. After you create the cell, as you did for the inverter, select Easy Edit and then Add Objects -> Cell. In the dialog box that results, type the logical name of the inverter block that you created (i.e., inv_cell). Then place the outline that appears somewhere in the buffer's layout. Do the same for the second inverter. Your layout should now look like something like this.
Finally, note that ports at one level of the hierarchy, become pins at the next level. Pins indicate where connections are expected to be made between cells at the same level of the hierarchy, while ports indicate where external connections will enter for the next level of the hierarchy (and/or for simulations, as we will see in Tutorial 6...). So to complete the buffer you need to do two things:
1. connect the output pin of the first inverter to the input pin of the second -- use metal-2.
2. create new VDD, GND, IN and OUT ports at the buffer level.
My final buffer cell looks like this.

A few more notes about navigating a hierarchy:

You can look into the internal aspect of a cell using the Peek operation in the Context -> Hierarchy menu. You can undo this and return to the external view of the hierarchy using the Unpeek operation.
You can change the editing Context in the hierarchical cell, using the Context -> Hierarchy -> Set Context operation. The "context" specifies the cell that you are currently editing. For example, if you want to change something in the inverter cell, as opposed to the buffer cell, you can use this operation to specify that you set the context in the "inv_cell" cell. Remember: any changes you make will be reflected in all instances of the inverter cell!
Finally, you can flatten a hierarchical cell. This operation should be used carefully, though, and only when necessary, since flat designs are harder to maintain and debug. You can flatten a design by selecting a number of cell instances and then using Othe menu Edit -> Flatten .