SIMULATING FULL-CUSTOM DESIGNS

This tutorial will guide you through the procedure of extracting the netlist from the buffer cell you created in Tutorial 4, and then simulating it with Accusim.

Netlist Extraction from a Layout Cell

Recall the buffer cell you created in Tutorial 4:

Before beginning, make sure the following conditions hold:

the cell must be surrounded by a green outline, the fp1 layer, from the IC Graph palette.
all the ports of the cell must be named and identified as input/output, and signal/power.

To do netlist extraction:

Select the IC Extract(M) pallete from the IC Palletes window .
Select Lumped (adequate for relatively small cells) from the pallete.
In the resulting dialog box select "Yes" at the Netlist button, and then enter a name for the netlist file. For example, the netlist name in this case might be buffer.sp. Also, enter GND as the Ground name. Note that the default format for the netlist is HSPICE. Click OK and the produced netlist will be saved in your Working Directory.
Take a look at the netlist. Notice the subcircuit definition:

.subckt buffer GND IN OUT VDD
The first argument is the name of the layout cell, and the following args are the input/output ports (including VDD and GND). This subcircuit statement defines the interface of the layout cell.
The body of the subcircuit is comprised of a list of device descriptions for the transistors that make up the cell. Each transistor description includes:
- an identifier which starts with "m" (because the transistors are MOSFETS)
- the four pins of the transistor (Drain, Gate, Source, and Bulk)
- a letter indicating the type of the transistor (n for NMOS, and p for PMOS)
- the length and the width of the transistor in micrometers
- the area of the drain and the source of the transistor. These areas are used from Accusim in order to calculate the parasitic capacitances of each transistor.
Below that you find the list of parasitic capacitances inherent to the subcircuit. For bigger cells w/ longer interconnections you would also find some resistive parasitics.

We are done with the extraction process and with IC Station. Before we can simulate the netlist with Accusim, however, we need to map the netlist to a logic symbol using Design Architect.

Logic Symbol for the Extracted Subcircuit

We now have to create a logic symbol on which to map the extracted subcircuit:

Start Design Architect (da).
Select Open Symbol, and specify a name for the logic symbol (e.g., buffer_sym).
Use the Add Rectangle and Add Pin buttons, in order to draw something like this. Specifically:
- Add input pins for all the inputs of your subcircuit (including VDD and GND).
- Add some text for the name of the symbol (e.g., Buffer). This is optional.
- Add the property ELEMENT with value X, because this symbol is mapped to an HSPICE subcircuit.
- Add the property MODEL with value buffer, the subcircuit name.
- Check, Save, and Close the symbol.

Logic Design to be Simulated

Now we have to create a schematic for the circuit that will be simulated with Accusim. Still in Design Architect:

Create a schematic, i.e., select Open Sheet.
Instantiate the logic symbol that you created in the previous step (buffer_sym), and draw a schematic something like this
- You can find the port, VDD, and GND symbols in the $MGC_GENLIB library.
- Specify that the VDD voltage is 3.3 Volts instead of 5.0 Volts.
- Use the Vss symbol for GND: rename it to GND and assign it the value of 0 Volts.
After you are done with this editing, Check, Save, and Close this schematic.

Of course, the logic diagram need not be so simplistic. It could include arbitrarily many symbols (mapped to the same or different layout-extracted subcircuits) and transistors from the sdl library (as in Tutorial 5).

NOTE: It seems that Accusim does not like busses and signal names that are `bus-like' (e.g. A(1), A(2), etc). If your design includes busses, use individual signals instead, and instead of giving the signal names in parenthesis, use something like A_1, A_2, etc.

Viewpoint

Use sdl_prep (see Tutorial 5) to create an accusim viewpoint for your schematic.

Accusim Simulation

You are (finally!) ready for the Accusim simulation:

At a command prompt, cd into the directory that contains your schematic and viewpoint and type:
where sdl is the name of the viewpoint created by sdl_prep.
Unfortunately, we have still not found an easy way to map the port order in the subcircuit that is extracted from the layout, to the pin order in the logic symbol that is mapped to this subcircuit. To solve this problem, you must do the following:
- Select File -> Write Netlist, and click OK in the resulting dialog box.
- In the window that pops up showing the Accusim netlist to be simulated, search for the statement that declares the buffer subcircuit, something like:
  Note the order with which the ports of the full_adder appear.
- Now, manually edit your netlist file (buffer.sp) so that the ports appear these in the same order, i.e., after the editing that netlist line should be:
Select File -> Auxiliary Files -> Load Netlist File. In the resulting dialog box, use the navigator to select the netlist buffer.sp.
Select File -> Auxiliary Files -> Load Model Library. In the resulting dialog box, type in $PROJ_PARTS_cs755/fets.mod.

Now you can setup Accusim for a Transient simulation, add the traces, apply some forces, and run the simulations, as described in Tutorial 5.