Fifth Tutorial

CMOS Circuit Design and Accusim Simulations

by

Constantinos Dovrolis

University of Wisconsin, Madison

Spring 1999.


Overview

In this tutorial you will learn how to simulate circuit designs using the Mentor toolset. The circuit designs will be using the MOS transistor models of the scmos process for the case of a 0.8 micron technology. The circuit schematic will be drawn using Design Architect. Then, an Accusim viewpoint will be created in order for the circuit design to be `readable' from Accusim. Finally, the circuit will be analyzed using the analog simulator Accusim. This procedure will be explained using the example of a transmission-gate 2-input XOR gate. The emphasis will be given on the Accusim simulations, since it is assumed that the reader is already familiar with Design Architect.


Circuit Schematic

In several cases, and especially in the case of components with critical timing requirements, the designer prefers to work on a transistor-based circuit, rather than on a gate-based logic diagram. This allows more flexibility in the selection of the circuit structures that implement a desired operation. Suppose that we want to analyze the transmission-gate-based 2-input XOR gate that follows:

Note that if A=0 the output O is driven by the input B through the transmission gate. If A=1, the output O is set to the complement of B. This implements a 2-input XOR gate with only 6 transistors. Note that the VDD supply is set to 3.3V and that all the transistors have minimum length (2 lambda). Also, all the PMOS transistors have double width than the NMOS transistors.

In order to simulate the timing behavior of this gate more realistically, we will assume that it drives an inverter with the same transistor dimensions as the XOR gate. The two transistors that make up this inverter create the load for the output of the XOR gate. Consequently, the schematic that we want to simulate is as follows:

At this point you can enter this schematic yourself. You need to run Design Architect and open a new sheet named, say, tg-xor2. Then select Choose Symbol and use the Navigator button to go to the following directory:

$MGC_HEP/lib/sdl

This is the library of MOS transistors for the scmos process. Design the circuit using the nmos3, pmos3, vdd, and vss symbols. You can find the port symbols (portin and portout) in the $MGC_GENLIB library. Connect these symbols as shown in the above schematic. Do not forget the following steps:

  1. Change the VDD voltage from 5V to 3.3V. In order to this, select the VDD symbol and then modify the value of clicking the right mouse button and selecting the menu Properties->Modify.
  2. Change the width of the PMOS transistors in the same way (i.e., select the transistors and change the width property that determines the transistor widths; you can do this for either one transistor at a time or for all of them).
  3. Name the ports, for example, as A, B, and O.
  4. Check the design. If you have any errors, try to fix them. You can ignore however any warnings that relate to the parameter lambda. This parameter will be specified when we create the design viewpoint.

Save the design and exit Design Architect.


Viewpoint Creation

Before we are ready to simulate a circuit design with Accusim, however, we need to create a design viewpoint that `binds' this design with certain technology-specific properties that are required for Accusim simulations. In order to do so, we will be using a script called sdl_prep, written by Dave Zar of Washington University. Copy this script in a directory that is in your Unix path (you need to do this, of course, only once).

In order to run sdl_prep go to the directory in which you have stored the tg-xor2 design, and run:

sdl_prep tg-xor2

Note that you only need to run this script for a particular design once, as long as you don't change the design. If you do change the design, however, remove first the design viewpoint that sdl_prep creates (using Design Manager) and then run sdl_prep again.


Accusim Simulations

You can now run Accusim on the viewpoint that was created for the tg-xor2 circuit. You can invoke Accusim from the Design Manager. Run Design Manager and double-click on the Accusim icon in the Tools window. In the form that will appear use the navigator to select the sdl viewpoint of the tg-xor2 design.

After a while the Accusim window will appear, including a small window with the tg-xor2 design. Accusim is the major analog simulator of Mentor Graphics and it supports a very wide range of simulation types. Although it is similar in principle with the Berkeley SPICE simulator, it is significantly more powerful and user-friendly than SPICE. In addition, it allows the designer to select different simulation algorithms, exploiting the trade-offs between simulation accuracy and speed.

We first need to setup Accusim for Transient analysis. Click on the Setup Analysis button, and in the form that will appear, select Transient. The Stop Time can be set to 100N (for nanoseconds), while the Maximum Time Step can be set to 1N. The form should be as follows:

Now, we have to specify the forces (i.e., input waveforms) for each input. First, select the input A from the window with the circuit schematic. Then click on the Add Force icon, and in the form that will appear select the following:

Reference (voltage): VSS
Force Type: PULSE
Delay Time: 0
Rise Time: 0.1N
Fall Time: 0.1N
Pulsed Value: 3.3
Pulse Width: 10N
Period: 20N

The form should be as follows:

Now, unselect input A and select input B. Provide the same force for input B but this time select the delay time to be 2.5N, the pulse width to be 5N, and the period to be 10N. You may want to experiment with different force types later. Of special interest is the PWL (Piece-Wise-Linear) Force Type.

At this point, select the two inputs A and B and the output O, and then click on the Trace button. A form with three traces will appear.

Before we run the simulation, we need to specify the library in which the Accusim models for the scmos MOSFET transistors will be found. Select the menu File->Auxiliary Files->Load Model Library . In the form that will appear, use the navigator to select the library $MGC_HEP/technology/accusim/fets.mod.

Now we are ready to run the simulation. Click on the Run button, and after a while the traces with the input and output waveforms will appear:

Note that the design is correct, since it behaves as an XOR gate. At this point you can experiment with different options/utilities of Accusim. First, you can measure rise/fall times and delays using the menu Results/Waveform Measurements - Transient. Measure the rise and fall times for the output O. Also, measure the delay between each of the inputs A and B and the output O.

An interesting feature of Accusim is that the design can modify certain transistor parameters `on-the-fly', and rerun the simulation. For example, you can select all the PMOS transistors of the design and then click on the Design Change button. Then, click on Change Property, and select the width property of the transistors, giving a new value that you want to simulate. At that point you can rerun the simulation until you get satisfactory timing behavior. After you decide in this way which are the appropriate dimensions of the circuit transistors you can go to IC Station and create a full-custom or SDL layout based on the transistor dimensioning that you did with Accusim.


Accusim has many more features and capabilities and during the semester we will use several of them. Of special interest are the Simulator Setup Options which determine the algorithms and parameters that Accusim uses in the simulation process. Accusim can be configured using those options to work with the same accuracy as SPICE, or just as a switch-level simulator, or in a wide variety of intermediate accuracy settings.