Brad Beckmann,
University of Wisconsin, Madison
1/25/01

Preface

This tutorial is designed to take you through the process of creating, compiling, and simulating your .vhdl source files.  You will create a .vhdl text file with a simple design, compile and debug your design, and then simulate your design using modelsim.
 
 

Editing and Compiling .vhdl files

This first step of the process is much like designing and compiling any other program with just a couple additions.
 

• Create a .vhd file in your favorite editor and save it to your hdl directory.  In this example you can just copy this vhdl file of a 4 bit ripple adder. ripple_adder.vhd
• Now you need to map the Logical HDL library to a physical one.  In this step you will create and modify a file named modelsim.ini.  This file is needed by the modelsim simulator, so it can not be skipped.  Enter the line % vlib $DESIGNS/tutorial/hdl/work followed by the line % vmap work $DESIGNS/tutorial/hdl/work  These lines will create a working directory /work under your hdl directory.  This work directory will contain the model needed by modelsim to simulate your ripple_adder design.
• Compile your file with the line % vcom ripple_adder.vhd
• Oh no!  The darn semi-colon error.  Add the missing semicolon and recompile the .vhd file.
• Before we start simulating our design, we have to do one more Logical to Physical mapping.  This virtual library will be used by the synthesizing tool, leonardo, in the next tutorial.  Enter the line % vlib $DESIGNS/tutorial/adk followed by the line % vmap adk $DESIGNS/tutorial/adk
• Compile the adk.vhd file into the adk work directory with the line % vcom $ADK/technology/adk.vhd -work adk
• Now that our file compiles, we can move on to simulating our design.

• Invoke ModelSim by the line % vsim ripple_adder &
• The QuickStart menu should appear.  Pretty bold claim, uh.  Let's hope ModelSim can live up to it.  If the QuickStart menu does not appear, you can access it thru Help->Quick Start Menu.  Click on See An Example for an indepth 43 step demo and select Simple VHDL Project.  This tutorial will only briefly go thru the simulation process.
• Close the QuickStart menu.  Go to the main menu and select view->all.  Be dazzled as a bunch of windows will appear.
• Type view source at the command line.  The ripple_adder.vhd source file should appear in the screen.
• Type add wave -r * followed by add list -r * at the command line.  The signal names should appear in the waveform viewer.
• Now we have to force our input signals.  Type the following four lines in the command line:

• Type run at the command line.  The simulation will run for the default 100 ns.  Your output waveform should look like this. wv100.ps
• Type run 300 at the command line.  Now the total time diplayed in the waveform window is 400 ns.  Once you are convienced that the design works, exit ModelSim.

Now that we are assured our design works, we are ready to synthesize it using the leonardo tool.