Automatic Layout from a Schematic

Brad Beckmann
University of Wisconsin, Madison
1/27/01



 

Preface

Now we will automatically generate layour for our 4-1 mux.  This tutorial will only give you an overview of the place & route tool.  You should make yourself more familar with the tool beyond the tutorial.
 
 

Using IC to Generate Layout from a Schematic

NOTE YOU WILL NEED TO WAIT 10-15 MINUTES FOR THE LIBRARY TO LOAD!!!


At this point, you have completed the automatic layout of your multiplexer. Many options for viewing the results of this process exist. Among them:

   1.Double click middle mouse button to pan view
   2."Z" stroke from top to bottom to zoom out, from bottom to top to zoom in
   3.view->all from the top menu bar to fill the screen with the design

You are encouraged to create the layout of this design using different options for the floorplanning, placement, routing, and compaction. As you will see, the resulting layout can be quite different in terms of area consumption. For example, the following two layouts were produces using different IC Blocks options.
 
 

Layout Verification

Although the automatic tools performed the layout in the Correct-by-Construction mode, it is always a good practice to verify the layout for correctness in terms of both layout design rules and connectivity, in order to insure consistency between the various tools used. This establishes a system of "checks and balances" that increases our overall confidence in the design. We will first check for layout design rule errors using IC Rules, and then verify the layout by double checking it against the logic level representation of the mux logic diagram.
 


           Overlap of N+ and P+ not allowed.
 

The design rule checker is complaining about p-select and n-select mask layers being too close. This error is an artifact of how the cell library was generated. Just ignore it for now. Also, the tool may report that the p-substrate that we use does not have any substrate contacts. You can ignore this too at this point.
             Ground Names : VSS GND
 
Press OK in both forms.
Backannotation for QuickSim

You will now backannotate the Quicksim viewpoint with post-layout capacitive
parasitics. The resulting Quicksim simulations will be more realistic, since they will be
modeling interconnect capacitances.
 

         dve ami05
 


Before you close IC Station save your completed layout cell by selecting File -> Cell
-> Save Cell -> Current Context.
 

Backannotation for Accusim


Post-Layout Accusim Simulations