CS/ECE 755: VLSI Systems Design
Spring 2002 Offering
Office: 6369 CS
Office hours: Tuesday and Wednesday 1:30-2:30, or by appt.
Office phone: 263-7463
Office: 1338 CSS
Office hours: Friday 2.00pm - 4.00pm
Office phone: 262-6592
Table of Contents
What's New in Class
First lecture will be Wednesday, January 23rd.
Friday, January 25th will be a discussion section on the tools led by Pranay.
Course times: MWF 11:00am--12:15pm
Lecture room: 3534 Engineering
Midterm Exam: Wednesday, March 20th, in class
Final Exam: Friday, 2:45pm, May 17th, 2002
Room 1263 Computer Sciences
Introduce students to trade-offs in modern MOS technologies, and their
impact on computer architecture and microarchitecture.
Introduce students to the CAD tools needed to manage the complexity of
Get a feel for the types of chips to be designed in the next century.
In this course we will study the design of digital systems using MOS circuits,
with an emphasis on architectural and micro-architectural trade-offs. We
will treat the subject as a natural outgrowth of digitial system architecture,
and will not assume any background in semiconductor devices. This course
will have a different emphasis than when it is taught by the ECE faculty.
When taught in ECE, the course emphasizes circuit design, circuit optimization,
and CAD algorithms. In this course, we will touch on each of these areas,
but spend more time focusing on the architectural aspects of VLSI systems
design. We will examine the impact of VLSI technology on contemporary processor
and memory system designs.
This is NOT a circuits course
CAD Tools and Computers:
We will be using the Mentor Graphics CAD tools. These are extremely powerful
commercial tools. However, they have a "large learning curve," and we anticipate
some problems. Students should take this into account when starting individual
assignments and their project. There will be considerable leeway granted
if there are widespread problems with the tools, however, failing to leave
sufficient time before the due date is not a valid excuse. The computers
assigned for the course are the color Suns in the Computer Sciences Instruction
labs (e.g., Room 1358, 1368, and 1347/1349 CSS). If you are not familiar
with UNIX, you should attend one of the UNIX orientation sessions given
during the first two weeks of classes.
ECE students will also have accounts on the CAE machines. Most of the
tools will be available at CAE, although there may be minor differences
in the configurations. We will try to minimize these as much as possible.
Although the details of the design tools will not be covered in class,
the TA will organize several additional recitation sections to help you
Exams:There will be both a midterm exam and a final exam. The midterm
will cover all material upto the exam. Both exams will cover all the material
in the text, lectures, and assigned readings. Both will be two hour exams
held outside of class hours.
Homework: There will be 4-5 assignments in the first half of the
semester. These assignments are geared towards introducing you to the design
tools and technology as well as making sure you know the material. Assignments
will not be weighted equally; the approximate weight of each assignment
will be specified when it is handed out. Assignments are due at the end
of class; however, you are expected to be in lecture, on time, when homework
is due. Failure to complete homework assignments can have a significant
negative impact on your grade. Except when explicitly stated otherwise,
all assignments must be done individually. You are encouraged to discuss
the assignments with your peers, but YOU MUST WRITE UP YOUR ASSIGNMENT
INDIVIDUALLY AND IN YOUR OWN WORDS.
Project: During the second half of the course, you will work in
groups of 2-4 students to design, layout, and simulate a project. You are
free to choose your own group, subject to instructor approval. If possible,
your group should contain at least one CS student and one EE student. I
will give you a handout describing the overall project design. You will
be responsible for the detailed design decisions, implementation, and simulation.
Alternatively, you can pick your own project, subject to instructor approval.
Past experience indicates that the project will be very time consuming,
but also very rewarding. Students should also be aware that the tools may
have some bugs (or simply just be hard to learn how to use correctly).
We will do everything we can to minimize the inconvienences, but students
should plan to leave time for unanticipated problems.
Presentation: The last week of lectures will be used for in-class
||Overview, MOS as an Abstract Technology, CAD
||MOS Transistors and Gates, Delay Estimation
||Topology, PLAs, Catchup
||Sequential logic, Datapaths
||Billion Transistor Chips
||Low Power Design
||Final Exam, 2:45pm
Text and Reader
Principles of CMOS VLSI Design -- A Systems Perspective, Neil H.
E. Weste and Kamran Eshraghian, 2nd Edition, Addison-Wesley, 1993 ISBN
DRAFT Course reader (on-line) This
will eventually be a collection of 10-15 papers.
Spring 2002 Project
General project information
Projects from prior years
2001 project description
Reference for Spring 2001 project:
Snooping: Building an Asynchronous SMP, Milo M. K. Martin, Daniel J.
Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J.
Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. In
the 9th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS), November 2000.
Spring 2000 Course Project: Version
Spring 2000 Course Project Schedule
Spring 1999 project: VLSI design of a
4-port Crossbar Switch based on Virtual-Output-Queueing
Tutorials on CAD Tools
Spring 2002 tutorials:
Spring 2001 tutorials:
Creating Automatic Generated Layout from a HDL file
Creating Automatic Generated Layout from a Schematic
Creating Full-custom Layout
Spring 1999 tutorials:
Spring 2000 tutorials:
Supporting Material for the CAD Tools
Spring 2001's discussions:
Spring 1999's discussions:
Spring 2000's discussions:
Discussion 1: (Feb-15, 1999) The
overall toolset picture, some layout examples, and the standard-cells methodology.
Discussion 2: (Feb-22, 1999) More
on Placement, Routing, Backannotation. Circuit Simulations with Accusim..
Discussion 3: (Mar-1, 1999) More
on Full-Custom Layout Editing, Hierarchical Layout, IC Extraction..
Discussion 4: (Mar-15, 1999) More
on LVS, and Schematic-Driven-Layout..
Discussion 5: (Mar-22, 1999) Three
processor implementations: MIPS R10000, DEC 21164, HP PA8000.
Discussion 6: (Apr-5, 1999) The
evolution of Alphas, and a PowerPC with copper interconnects.
Discussion 7: (Apr-14, 1999) A
Sum-Addressed-Memory-Cache, and a Fully Parallel CAM.
Discussion 8: (Apr-21, 1999) Inside
the Rambus Interface .
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