Piranha

Recognized trends

• substantial increases in design times
• diminishing returns in SPEC
• DB/Web fastest growing market
• • large mem. stall and comm. misses
  • lots of thread-level parallelism

Piranha Node

• 8 Alpha cores
• • single-issue in-order 8-state pipeline
  • private I&D caches
• Shared L2 cache -> 8 banks, each attached to memory controller
• Glueless, no I/O on standard Piranha (use separate I/O chips)
• KEY POINT
• • 2/3 of bandwidth to other Piranhas, 1/3 to memory
  • possibly motivated by scaling to 1000s of nodes
  • is this right?

Interchip Connection Network

• internal in-order cross-bar

L2 Cache

• non-inclusive
• enforces coherence
• L1 shadow tags maintained