CS838 Summary

Motivation

• ITRS Roadmap
  • System On a Chip (SOC) - breakdown of logic vs. memory
  • 52% mem in 2002, 71% mem in 2005, 94% mem in 2014
• Are these assumptions realistic?
  • Logic vs. memory breakdown makes many assumptions about computation vs. communication ratio
  • Authors are technologists, not visionaries

Goal: provide speed of SRAM, density of DRAM

• Makes DRAM look like SRAM
• Intended for systems with > 0.25 Mb memory
  • Incremental size disadvantage of 6T-SRAM negligble below this point
• Two technology options:
  • standard CMOS process: 2X density of 6T-SRAM
  • modified CMOS process: 4X density of 6T-SRAM

Making It Fast

• Very small block size
  • lower bitline & wordline capacitance => higher speed
  • Multiple blocks combined into macrocell
• Also uses fast address decode logic

Hiding Refresh Latency

• Macrocell organized into banks
• 1 SRAM cache block per macrocell, same size as a bank
• Banks can be refreshed while reads to other banks are served
• Worst-case scenario: All reads go to same bank, but don't touch some rows
  • Solution: refresh time of bank < time to read entire bank
  • Thus, guaranteed to have a cache hit during "proper refresh period" (refresh time / # rows)
• David's question: do we care about hiding refresh latency for an on-chip L2 cache?
  • Maybe- we might want deterministic hit times for aggressive scheduling
  • But, refresh operations occur with known frequency, so we can account for this in scheduling

Process Technology

• Standard CMOS process: uses horizontal plate cap, defined by poly gate mask.
• Modified CMOS process: uses "Folded Area Capacitor (FAC)" - a vertical capacitor to reduce cell size
  • Requires additional non-critical mask step, an additional etch step (to create trench in STI) and an additional dep step (to fill the trench with polysilicon).