My research interests lie in the intersection of computer architecture, parallel systems, and application analysis. I am presently working with Professor Karu Sankaralingam investigating application-level fault tolerance and system-wide techniques to exploit this tolerance in emerging platforms. I also recently completed a port of the MapReduce programming model to the Cell B.E. processor architecture.
September 25th, 2008
Passed my qualifiers! Glad to have that out of the way.
November 8th, 2007
Under "Publications" I have added a link to a Technical Report detailing the design and performance of the MapReduce for Cell runtime as of sometime in August. Performance for some types of applications can be significantly improved, and the technical report details some of the challenges and also suggests a hypothetical performance upper bound. I leave it to anyone interested to build on this work and realize its full potential. The code is available on sourceforge.net, distributed under the MIT license.
Sept 26th, 2007
My implementation of MapReduce for the Cell achieved 2nd place in the IBM Cell B.E. Challenge '07! The press release is available here. The quoted performance numbers are actually a little embarassing. At the time of submission the evaluation suite was very limited. Today, tuned SIMD applications have much more respectable performance numbers.
M. de Kruijf and K. Sankaralingam.
MapReduce for the CELL B.E. Architecture.
IBM Journal of Research and Development 53:5. 2009.
M. de Kruijf and K.Sankaralingam.
Exploring the Synergy of Emerging Workloads and Silicon
Reliability Trends.
SELSE '09: IEEE Workshop on Silicon Errors in Logic –
System Effects, March 2009.
M. de Kruijf and K. Sankaralingam.
MapReduce for the Cell B.E. Architecture.
University of Wisconsin Computer Sciences Technical Report CS-TR-2007-1625,
October 2007.
Talk: ppt