UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department
CS 537
Spring 2001 		A. Arpaci-Dusseau
Quiz #6: April 4th -- Memory Management
Name: Student ID #:

Problem 1: Stacks vs. Heaps (21 points, 3 pts each)

Specify whether each of the following statements applies more to stack or heap allocation. Specify only one. 

_________ Appropriate for any sequence of allocations or frees

_________ Manipulated with malloc() and new()

_________ Appropriate for procedure call frames

_________ Fast and efficient

_________ Keeps all free memory contiguous

_________ Can lead to external fragmentation

_________ Allocation algorithms include best-fit and first-fit

Problem 2: Multiprogramming Memory(48 points, 6 pts each)

Match each of the following statements with the most relevant approach for supporting the multiprogramming of memory. Specify only the most appropriate approach. (Do not consider combinations of approaches, for example, segmentation with paging. Do not consider the impact of a TLB.) 
a.  Static Relocation
b.  Dynamic Relocation
c.  Segmentation
d.  Paging

______ Requires no hardware support

______ Causes no external fragmentation

______ Requires that the entire address space is allocated contiguously

______ Provides no protection across address spaces

______ Cannot move address spaces after they have been placed

______ Requires only base and bounds registers in MMU

______ Enables efficient allocation of sparse address spaces

______ Requires additional memory accesses for address translation

Problem 3: Address Formats (31 points)

Consider a logical memory architecture with the following parameters: a) Draw how the logical address is partitioned (i.e., the number of bits used to designate segments, pages, and page offset). Don't worry about having page tables fit within a page.
b) Now worry about having each page table fit within a page. Assume that each page table entry contains a read and a write protection bit and that the maximum amount of physical memory supported by the architecture is 8MB. Redraw the logical address, showing the number of bits used to index into each level of the page tables.

(Hint: You need to calculate the size of each page table entry. As an intermediate step, you may find it helpful to calculate the number of pages that fit in physical memory. Then, how many bits in each PTE are needed to designate one of these pages? Add the two bits for read and write protection to determine the size of each PTE.)