Name:

Student ID #:

Memory Management: Segmentation and Paging

Problem 1: Address Translations (30 points)

Translate the following logical addresses to 24-bit physical addresses (briefly describe any errors).

a) Read 0x002070: Segment: 0, VPN: 2, offset: 070 --> 0x003070

b) Write 0x201016: Segment: 2, VPN: 1, offset: 016 --> 0x00b016

c) Read 0x204014: Segment: 2, VPN: 4 - Page out of bounds error

d) Read 0x101c84: Segment: 1 - Read protection violation (or out of bounds error)

e) Read 0x003fd4: Segment: 0, VPN: 3, offset: fd4 --> 0x011fd4

f) Write 0x002424: Segment: 0 -- Write protection violation

Problem 2: Implications of Address Format (40 points)

calculate the following properties of the memory system. You should give your answer both in terms of a power or 2 (e.g., 2^15 bytes) and written out in terms of KB or MB (e.g., 32KB).

a) Number of segments: 2^2 = 4

b) Maximum size of each segment: 2^24 bytes = 16MB

c) Size of each page: 2^8 bytes = 256 bytes

d) Maximum number of pages per segment: 2^16 pages = 64K pages

e) Maximum size of each page table (per segment).
Assume each page table entry (PTE) requires 4 bytes.

2^16 entries * 4 bytes/entry = 2^18 bytes = 256K bytes

Problem 3: Paging Page Tables (30 points)

Imagine that you are building a memory management system in which you want each page table to fit within a single page in physical memory. As you know, this requires multiple levels of page tables.

a) Show how you would divide the logical address such that each page table fits on a page. Please show any necessary calculations.

We need to divide the logical page number such that each set can be used to index into a page table that fits in a single page. The main question then, is how many page table entries (PTEs) fit on a page:

2^8 bytes / (4 bytes/entry) = 2^6 entries.

Therefore, at most six bits can be used to index into a page table.

We apply this recursively to the logical address so that each level of page tables fit in a page. Thus, there will be one more page table with 2^6 entries. At this point, there are only (16-6-6=4 bits) remaining in the logical page number, so the last level will have only 2^4 entries in its page table, requiring 4 bits of the page number.

This leads to:

The high-order 4 bits of the page number are used to index into the outer-most page table; this then points to the base of another page table. We use the next set of bits to index into this second page table, and so forth. Note that we will still have 2 bits for the segment number (this is a fixed part of the architecture).

b) With this new structure, how many memory references are needed to translate a logical address to a physical address? (Assume that there is no Translation Lookaside Buffer.) Briefly explain each memory reference.

Three memory references are required to get the physical address.

We get the base of the outermost page table from the Segment Table; the Segment Table is very small (4 entries), so can be kept in registers, not requiring a memory reference.

First memory reference: Use outer page table (indexed by top 4 bits) to lookup base of middle page table.

Second memory reference: Use middle page table (indexed by next 6 bits) to lookup base of inner page table.

Third memory reference: Use inner table (indexed by last 6 bits of the page number) to get the physical page number (PPN). The 8 bit offset will be appended to this to the PPN to generate the final physical address.