UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department
CS 537
Spring 2001 		A. Arpaci-Dusseau
Quiz #6: April 4th -- Memory Management
Name: Student ID #:

Problem 1: Stacks vs. Heaps (21 points, 3 pts each)

Specify whether each of the following statements applies more to stack or heap allocation. Specify only one. 

_Heap_ Appropriate for any sequence of allocations or frees

_Heap_ Manipulated with malloc() and new()

_Stack_ Appropriate for procedure call frames

_Stack_ Fast and efficient

_Stack_ Keeps all free memory contiguous

_Heap_ Can lead to external fragmentation

_Heap_  Allocation algorithms include best-fit and first-fit

Problem 2: Multiprogramming Memory(48 points, 6 pts each)

Match each of the following statements with the most relevant approach for supporting the multiprogramming of memory. Specify only the most appropriate approach. (Do not consider combinations of approaches, for example, segmentation with paging. Do not consider the impact of a TLB.) 
a.  Static Relocation
b.  Dynamic Relocation
c.  Segmentation
d.  Paging

_a_ Requires no hardware support

_d_ Causes no external fragmentation

_a,b_ Requires that the entire address space is allocated contiguously

_a_ Provides no protection across address spaces

_a_ Cannot move address spaces after they have been placed

_b_ Requires only base and bounds registers in MMU

_c_ Enables efficient allocation of sparse address spaces

_d_ Requires additional memory accesses for address translation

Problem 3: Address Formats (31 points)

Consider a logical memory architecture with the following parameters: a) Draw how the logical address is partitioned (i.e., the number of bits used to designate segments, pages, and page offset). Don't worry about having page tables fit within a page. 
Page size of 512 bytes = 2^9 bytes --> 9 bits for page offset

Segment size of 2MB = 2^21 bytes --> 21 - 9 bits = 12 bits for page number

24-bit logical address - 9 - 12 = 3 bits for segment number (i.e., 8 segments)

Logical address
b) Now worry about having each page table fit within a page. Assume that each page table entry contains a read and a write protection bit and that the maximum amount of physical memory supported by the architecture is 8MB. Redraw the logical address, showing the number of bits used to index into each level of the page tables.

(Hint: You need to calculate the size of each page table entry. As an intermediate step, you may find it helpful to calculate the number of pages that fit in physical memory. Then, how many bits in each PTE are needed to designate one of these pages? Add the two bits for read and write protection to determine the size of each PTE.)

If the maximum amount of physical memory supported by the architecture is 8MB, then each physical address has 2^23 bits. We know that each page is 512 bytes and thus 9 bits of the physical address are used for the page offset, leaving 14 bits for the physical page number (ppn). (Calculated another way, given that each page is 512 bytes, physical memory fits 2^14 = 16K pages, indicating 14 bits are needed for the ppn.)

Thus, each PTE is 14 bits (for the PPN) plus 2 bits (for the read and write protection) for a total of 16 bits or 2 bytes.

Given that each PTE is 2 bytes, we can now determine how many PTEs can fit on a page: 2^9 bytes / (2 bytes/entry) = 2^8 entries. Therefore, at most 8 bits can be used to index into a page table that fits in a single page. Thus, our 12 bits for the page number should be divided into one group of 8 and one group of 4.

Alteratively, if you didn't calculate the size of each PTE and simply assumed that it is 4 bytes (as we did in class), then you would determine that only: 2^9 / (4 bytes/entry) = 2^7 entries can fit on a page. Thus, the 12 bits for the page number should be divided into one group of 7 and one of 5.

Logical address