CS 537 - Quiz #8

	UNIVERSITY OF WISCONSIN-MADISON Computer Sciences Department
CS 537 Fall 2007		A. Arpaci-Dusseau
	Quiz #8: Nov 8 -- Take-home Due Tue, Nov 13

Name:

Problem 1 : Address Translation

Consider the following structure for a 24-bit logical address and contents for the segment table and page tables. Assume that Bounds is the number of valid PTE entries and that only the PPN within each PTE is shown.

Translate the following 24-bit logical addresses to their 24-bit physical addresses. Briefly describe any errors.

0x000730
0x101a34
0x40333a
0x802800
0xc01dd0
0x002568
0x100b8a
0x2fffff

Problem 2 : Format of Logical Addresses

Consider memory architecture with the following characteristics:

Byte-addressable (this is what we've always assumed in examples)
32-bit logical address
32 segments
Page size of 8 KB
Each page table entry (PTE) requires 8 bytes.

a) Draw how the logical address is partitioned (i.e., the number of bits used to designate segments, pages, and the page offset). Don't worry about having page tables fit within a page.

b) What is the maximum possible size in bytes of each segment? For all of the following questions, give your answer in terms of a power of 2 (e.g., 2^15 bytes) and in terms of K or M (e.g., 32 KB).

c) What is the maximum possible number of pages per segment?

d) What is the maximum size of each page table (per segment)?

e) How many PTEs can fit within a page??

f) Now assume that you need to ensure that each page table fits within a single page of physical memory by using multiple levels of pages tables. Draw how you would now divide the logical address, showing your intermediate calculations. (You must continue to support all of the original characteristics of the memory architecture.)