CS 701, Program 4
Graph Coloring Register Allocation

Due: Friday, December 12, 2014 (by midnight)

Not accepted after 11:59 pm on Wednesday, December 17, 2014

Overview

For this project you'll write one LLVM pass that does register allocation via graph coloring. You only need to handle code for which all live ranges get colored; handling uncolored live ranges (i.e., spilling) will be worth extra credit.

The LLVM pass that you write will be a MachineFunction pass, with this header:

bool runOnMachineFunction(MachineFunction &Fn)

You can find skeleton files in

/p/course/cs701-fischer/public/proj4/SKELETON

Type make to build the skeleton version of the register allocator. To run it (on a file called xxx.c), either type make XXX.reg, or:

    clang -emit-llvm -O0 -c xxx.c -o xxx.bc
    opt -mem2reg xxx.bc > xxx.ssa
    mv xxx.ssa xxx.bc
    llc -optimize-regalloc=0 -load Debug/lib/P4.so -regalloc=gc xxx.bc

Your MachineFunction pass will include the following steps:

1. For each register class RC, get the set of physical registers that can be allocated to RC.
2. Do reaching-definitions and live-variable analyses.
3. Compute initial and final live ranges.
4. Build the interference graph.
5. Color the nodes of the interference graph.
6. For each live range that is for a virtual register V, and that has an allocated physical register P:
   1. replace all instances of V in the live range with P, and
   2. save and restore P across all calls in the live range.
7. For extra credit:
   For each live range that is for a virtual register V that has no allocated physical register:
   1. allocate stack space for V;
   2. for each instruction I that includes an instance of V, find an appropriate spill register SR (one of the 3 spill registers for V's class that does not already occur in instruction I);
   3. replace all instances of V in I with SR;
   4. if V was used in I, then add an instruction before I to load from V's stackspace to SR;
   5. if V was defined in I, then add an instruction after I to store from SR to V's stackspace;

Step 4: Build the interference graph.

When building the interference graph, two (final) live ranges should be considered to interfere with each other iff

1. Their sets of CFG nodes are non-disjoint, and
2. Their sets of available registers plus the aliases of those registers are non-disjoint. Note that the live range for a physical register (a preg) has only itself as its "available register". The live range for a virtual register (a vreg) has as its "available registers" all of the physical registers that can be allocated to the register class of which that vreg is a member. (See Some Useful LLVM Operations below for how to get the register class of a vreg and how to find the aliases of a preg.)

Step 5: Color the interference graph.

Color the graph using the technique discussed in class: Iterate over all nodes of the graph (all final live ranges), pushing them onto a stack until all nodes are pushed, then pop all nodes, coloring them if possible.

Pushing nodes

Push all nodes that represent virtual registers before pushing any nodes that represent physical registers. First push all "easy" nodes: nodes that represent live ranges for virtual registers V whose number of unstacked neighbors is less than the number of registers available for V's register class.

NOTE: Do not double-count physical-register neighbors. If a virtual register has two or more neighbors that are live ranges for the same physical register, only count that as one unstacked neighbor.

If there are no "easy" nodes, push a node that represents a live range for a virtual register V that has a maximal number of unstacked neighbors -- don't do the extra work of computing the costs of not coloring live ranges. Again, don't double-count physical-register neighbors.

Note that pushing a node (whether easy or not) can cause other nodes to become easy.

Popping nodes

When a node that represents a physical register's live range is popped, its color should be the number of the physical register itself.

When a node N that represents a virtual register's live range is popped, its color should be a physical register number R such that the set that contains R and R's aliases does not overlap with the set that contains the registers allocated to N's popped neighbors and those registers' aliases. If there is no available register give an error message and quit. If you are doing extra credit, see below for how to handle uncolored live ranges.

Step 6(a): Replace instances of virtual registers with the appropriate physical register.

Given MachineFunction Fn and a pointer to an instruction inst whose k-th operand is a virtual register, replace that operand with physical register P using this code:

  const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
  MachineOperand &MOp = inst->getOperand(k);
  MOp.substPhysReg(P, *TRI);

Step 6(b): Handle Function Calls

You will need to add code to save the contents of physical registers across function calls. You can do this as follows:

1. When creating a live range, keep track of whether the range includes a call instruction. Given variable in, a pointer to a MachineInstr, use the following code to test whether the instruction is a call:

   const MCInstrDesc &MCID = in->getDesc();
   if (MCID.isCall()) ...
   

2. For each colored live range (for a virtual register V) such that the live range includes a call:

   • Allocate stack space in which to save the allocated physical register R across the call (do this just once for each live range that includes a call):

         MachineRegisterInfo *MRI = &Fn.getRegInfo();
         const TargetRegisterClass *RC = MRI->getRegClass(V);
         int frameIndex = Fn.getFrameInfo()->CreateSpillStackObject(RC->getSize(), RC->getAlignment());
     

   • For each call instruction I in the live range:

     • Generate code to store the current contents of the allocated preg R before the call

       // do these two assignments just once per function
       const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
       const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
       
       // do this for each call instruction I
       MachineBasicBlock *MBB = I->getParent();
       TII->storeRegToStackSlot(*MBB, I, R, true, frameIndex, RC, TRI);
       

     • Generate code to re-load the allocated preg R after that instruction (i.e., before the next instruction):

       MachineBasicBlock::iterator IT = I;
       IT++;
       TII->loadRegFromStackSlot(*MBB, IT, R, frameIndex, RC, TRI);
       

       Note that this works even if I is the last instruction in its basic block.

Setting aside Spill Registers

This step must be done before coloring the interference graph. For each register class, you will need to find 3 physical registers that are in the set of available registers for that class and do not occur explicitly in the program. Those 3 registers and all of their aliases must be removed from the available sets for all register classes. To avoid very poor use of registers (and risking not being able to complete register allocation), when you choose a spill register for one class, you should try to choose aliases of that register as the spill registers of other classes.

The Spill Registers will be used to replace instances of virtual registers in uncolored live ranges (we will call those "uncolored virtual registers"). Note: This discussion assumes that no machine instruction includes more than 3 distinct virtual registers. We believe this to be true. If your code is run on an example for which it is not true, and it causes your register allocator to fail, print an error message and quit. If you find such an example, please inform us.

Handling instances of uncolored virtual registers

After handling all colored live ranges (replacing all instances of the colored virtual register associated with that live range with the allocated physical register) you should handle all uncolored live ranges. To handle one uncolored live range whose associated virtual register is V, do the following steps:

1. Get stack space for V as follows:

     const TargetRegisterClass *RC = MRI->getRegClass(V);
     int frameIndex = Fn.getFrameInfo()->CreateSpillStackObject(RC->getSize(), RC->getAlignment()); 
   

2. For each instruction I in the uncolored live range that includes an instance of V, get a Spill Register R for V such that neither R nor any of its aliases already occur in I. If V occurs more than once in I, use the same Spill Register for all such occurrences.

3. Replace each instance of V in I with Spill Register R using the same substPhysReg method used to replace each instance of a colored virtual register with the allocated physical register.

4. If V occurs as a use in I (use MOp.isUse()to find out) you must generate code to load the value of V from the stack into your chosen Spill Register R. That code must come immediately before instruction I, and can be generated as follows:

   MachineBasicBlock *MBB = I->getParent();
   TII->loadRegFromStackSlot(*MBB, I, R, frameIndex, TRC, TRI);
   

   where TII and TRI are the same as those values used to save and restore registers across calls; I is (a pointer to) the instruction you're handling, R is the chosen Spill Register, TRC is the TargetRegisterClass for V (as above), and frameIndex is the stack space that you allocated for V.

5. If V occurs as a def in I, you must generate code to store the defined value into the stack space that you allocated. This code must come immediately after instruction I; i.e., it must come immediately before the instruction that follows I. Here is the code that generates a spill of the value in register R immediately before instruction nextI:

   TII->storeRegToStackSlot(*MBB, nextI, R, true, frameIndex, TRC, TRI);
   

   See the explanation of how to save registers across calls for how to compute nextI.

  for (MachineFunction::iterator MFIt = Fn.begin(); MFIt != Fn.end(); MFIt++) {
    for (MachineBasicBlock::iterator MBBIt = MFIt->begin(); MBBIt != MFIt-&ht;end(); MBBIt++) {
      // *MBBIt is a MachineInstr

      int numOp = MBBIt->getNumOperands();
      for (int i = 0; i < numOp; i++) {
        MachineOperand MOp = MBBIt->getOperand(i);

      MachineInstr *oneIns = MBBIt;
      oneIns->dump();

MachineRegisterInfo *MRI = &Fn.getRegInfo();
int vregClass = MRI->getRegClass(V)->getID() // what class is virtual reg V in

const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
MCRegAliasIterator *it = new MCRegAliasIterator(P, TRI, false);
while (it->isValid()) {
  // **it has type "unsigned"; i.e., it is a preg that is an alias of P
  ++(*it);
}

~cs701-1/HANDIN/YOUR-LOGIN/P4